Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/118434
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dc.titleDESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS
dc.contributor.authorLI YONG FU
dc.date.accessioned2015-01-13T18:00:09Z
dc.date.available2015-01-13T18:00:09Z
dc.date.issued2014-07-22
dc.identifier.citationLI YONG FU (2014-07-22). DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/118434
dc.description.abstractThis dissertation proposes new circuit design techniques for Successive-Approximation-Register (SAR) Analog-to-Digital Converters (ADCs) and capacitive-array Digital-to-Analog Converter (DACs). A dual-channel, con?gurable 4-to-10-bit SAR ADC is proposed and fabricated in 130-nm CMOS technology. It operates at a supply voltage of 0.6-V and achieves a maximum sampling rate of 250-kS/s and a FOM of 24-fJ/step. To reduce the area and power consumption per channel, the ADC uses a dual-capacitive-arrays DAC architecture and reuses multiple building blocks, such as the DACs, the comparator and the SAR logic, for the dual-channel ADC. To minimize the switching power consumption across all resolution modes, an energy-ef?cient charge-recovery switching scheme is proposed. It achieves a 3.6-to-77.5? reduction compared to the conventional charge-redistribution scheme. As the resolution of the ADC increases, the matching requirements for the unit capacitors (i.e., increase the area of the unit capacitor) and the number of unit capacitors in the conventional binary-weighted capacitive-array (CBW) DAC increases exponentially, thus increasing the area, the switching power consumption and the settling time in the DAC. Therefore, two methods are proposed to address these challenges in high resolution (>10-bit) capacitive-array DACs. First, a placement strategy is proposed to address the layout?s mismatches, where a matrix-adjustment method is proposed to optimize the size of the CBW DAC, different placement techniques and weighting methods are proposed for the placement of active and dummy unit capacitors. The resulting star-like placement increases the degree of dispersiveness (i.e., reduce random mismatch), reduces the ?rst-order oxide-gradient-induced mismatches and the second-order lithographic errors and achieves a more symmetrical routing compared to existing works. A homogenization method is also proposed to reduce the asymmetrical fringing mismatches among the cap0061006300690074006900760065002D00610072007200610079002C0020007400680075007300200069006D00700072006F00760069006E00670020007400680065002000730079007300740065006D00610074006900630020006D00690073006D00610074006300680020006200650074007700650065006E002000740068006500200063006100700061006300690074006900760065002D0061007200720061007900200061006E00640020007400680065002000640075006D006D007900200063006100700061006300690074006F00720073002E000D000A000D000A005300650063006F006E0064002C002000740077006F0020006E006500770020007400790070006500730020006F0066002000730070006C0069007400200063006100700061006300690074006900760065002D006100720072006100790020004400410043002000610072006300680069007400650063007400750072006500730020006100720065002000700072006F0070006F00730065006400200074006F0020007200650064007500630065002000740068006500200061007200650061002C002000740068006500200070006F00770065007200200063006F006E00730075006D007000740069006F006E00200061006E006400200069006D00700072006F0076006500200074006800650020006C0069006E00650061007200690074007900200063006F006D0070006100720065006400200074006F00200074006800650020004300420057002000440041004300200061006E0064002000740068006500200063006F006E00760065006E00740069006F006E0061006C002000620069006E006100720079002D00770065006900670068007400650064002000730070006C0069007400200063006100700061006300690074006900760065002D0061007200720061007900200077006900740068002000610020006600720061006300740069006F006E0061006C00200061007400740065006E0075006100740069006F006E00200063006100700061006300690074006F00720020002800420057004100290020004400410043002E00200041002000640065007300690067006E0020006D006500740068006F0064006F006C006F00670079002000690073002000700072006F0070006F00730065006400200074006F002000640065007400650072006D0069006E006500200074006800650020007300650067006D0065006E0074006100740069006F006E002000640065006700720065006500200069006E0020007400680065002000440041004300200066006F00720020006F007000740069006D0075006D00200070006500720066006F0072006D0061006E00630065002E00200046006F007200200061002000310032002D00620069007400200053004100520020004100440043002C0020007400680065002000700072006F0070006F007300650064002000440041004300730020007200650064007500630065002000740068006500200069006E0070007500740020006C006F00610064002000630061007000610063006900740061006E0063006500200061006E0064002000610072006500610020006200790020003200D700200061006E00640020003400D7002C00200072006500730070006500630074006900760065006C0079002C00200061006E0064002000740068006500200073007700690074006300680069006E006700200070006F00770065007200200062007900200031003500D700200061006E0064002000310035002E003500D7002C00200072006500730070006500630074006900760065006C0079002C00200063006F006D0070006100720065006400200074006F002000740068006500200043004200570020004400410043002E00200049007400200061006C0073006F00200069006D00700072006F00760065007300200074006800650020006C0069006E006500610072006900740079002C0020006D0069006E0069006D0069007A0065007300200074006800650020006D00690073006D006100740063006800200076006100720069006100740069006F006E00200061006E006400200072006500640075006300650073002000740068006500200073007700690074006300680069006E006700200070006F00770065007200200062007900200033002E0037003500D700200061006E006400200033002E0038003700D7002C00200072006500730070006500630074006900760065006C0079002C00200063006F006D0070006100720065006400200074006F002000740068006500200042005700410020004400410043002E000D000A
dc.language.isoen
dc.subjectLow-Power, Low-Voltage,Successive-Approximation,Analog-to-Digital Converters, Digital-to-Analog Converters
dc.typeThesis
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.contributor.supervisorLIAN YONG
dc.description.degreePh.D
dc.description.degreeconferredDOCTOR OF PHILOSOPHY
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Ph.D Theses (Open)

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