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Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/112980
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dc.titleOverlap clocking technique for 10 bit 50MHz 3V D/A converter
dc.contributor.authorBhatt, Ansuya
dc.contributor.authorSingh, Raminder Jit
dc.contributor.authorTan, Khen-Sang
dc.date.accessioned2014-11-28T08:12:57Z
dc.date.available2014-11-28T08:12:57Z
dc.date.issued1995
dc.identifier.citationBhatt, Ansuya,Singh, Raminder Jit,Tan, Khen-Sang (1995). Overlap clocking technique for 10 bit 50MHz 3V D/A converter. International Symposium on VLSI Technology, Systems, and Applications, Proceedings : 361-364. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/112980
dc.description.abstractA 10-bit high-speed Digital-to-Analog (D/A) converter with small silicon area has been designed and fabricated using a new technique of overlap clocking for current switching to achieve low glitch energy. Common centroid layout technique has been used to achieve 10-bit accuracy without using any trimming. The D/A converter achieves 30 pV.s glitch energy while operating at 50 MHz with 3V supply.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentINSTITUTE OF MICROELECTRONICS
dc.description.sourcetitleInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
dc.description.page361-364
dc.description.coden220
dc.identifier.isiutNOT_IN_WOS
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