Border-trap characterization in high-κ strained-Si MOSFETs
Maji, D. Duttagupta, S.P. Rao, V.R. Yeo, C.C. Cho, B.-J.
Maji, D.
Duttagupta, S.P.
Rao, V.R.
Yeo, C.C.
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Abstract
In this letter, we focus on the border-trap characterization of TaN/ HfO2/Si and TaN/HfO2/strained-Si/Si0.8 Ge0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-κ films on strained-Si/ Si0.8Ge0.2. These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-κ films on strained-Si are also proposed. © 2007 IEEE.
Keywords
1/f noise, Border traps, Charge pumping, Hysteresis, Interface trapping, Strained-Si
Source Title
IEEE Electron Device Letters
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Series/Report No.
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Date
2007-08
DOI
10.1109/LED.2007.902086
Type
Article