Self-Aligned Source and Drain Contact Engineering for High Mobility III-V Transistor

ZHANG XINGUI

Publication

Self-Aligned Source and Drain Contact Engineering for High Mobility III-V Transistor

ZHANG XINGUI

Abstract

Driven by tremendous advances in lithography the semiconductor industry has followed Moore?s law by shrinking transistor dimensions continuously for the last 40 years. The big challenge going forward is that continued scaling of Si transistors will be more and more difficult because of both fundamental limitations and practical considerations as the transistor dimensions approach 10 nm. Among several emerging nanoscale devices, III-V MOSFETs are the most attractive devices due to their high electron mobility, low supply voltage, and potential heterogeneous integration on Si substrates. To take the full advantages of III-V MOSFETs, low-resistance source/drain (S/D) is required. However, III-V transistors currently have large S/D series resistance limiting the device drive current as they lack advanced S/D contact technologies. This thesis documents work performed on self-aligned S/D contact engineering for III-V n-MOSFETs. In this thesis, novel self-aligned metallization, analogous to the salicidation process in Si CMOS, was developed for III-V n-MOSFETs to address the high S/D resistance issue. New contact materials such as NiGeSi, Ni-InGaAs were developed and the key characteristics of these new contact materials were determined and identified. Various process integration challenges for realizing self-aligned S/D contacts were identified and addressed. Technology demonstrations of these new materials integrated as III-V S/D contacts in a self-aligned manner were also realized. In particular, NiGeSi and Ni-InGaAs were integrated in GaAs and InGaAs planar n-MOSFETs, respectively, using a salicide-like process and leading to reduced series resistance. For achieving better electrostatic control than planar n-MOSFETs, novel III-V FinFETs were explored. S/D resistance engineering was also carried out for the FinFETs. With well designed FinFETs structure and metallization process, self-aligned contacts such as Ni-InGaAs and Mo were realized on in-situ heavily doped III-V S/D. The combination of heavily doped S/D and self-aligned contacts leads to low series resistance for InGaAs FinFETs. Series resistance as low as 250 ohm??m was obtained, and this is the lowest value reported-to-date for InGaAs non-planar n-MOSFETs. This affirms the effectiveness of the S/D resistance engineering concept of combining heavily doped S/D and self-aligned contacts. The availability of self-aligned contact technology is an important step towards realization of high performance III-V logic transistors.