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GATE DIELECTRIC BREAKDOWN - 2D MODELING OF THE DBIE IMPACT ON THE DEVICE CHARACTERISTICS
CAO YU
CAO YU
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Abstract
A model based on the simulation of NMOS structures has been developed to study the experimental observation on the failure mechanisms of ultrathin dielectric gate breakdown during constant voltage stress. It is verified that the dielectric breakdown induce epitaxy (DBIE) plays an important role in the device electrical behavior after breakdown. Our model is helpful in the study of the breakdown types under different stress conditions.
Keywords
gate oxide, dielectric breakdown, dielectric breakdown induced epitaxy (DBIE), simulation
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Date
2003
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Thesis