Lee Sungjoo
Email Address
elelsj@nus.edu.sg
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Publication High-speed metal-germanium-metal configured PIN-like Ge-photodetector under photovoltaic mode and with dopant-segregated Schottky-contact engineering(2008-12-01) Zang, H.; Lee, S.; Yu, M.; Loh, W.Y.; Wang, J.; Lo, G.-Q.; Kwong, D.-L.; ELECTRICAL & COMPUTER ENGINEERING; PHYSICSIn this letter, we present a high-speed metal-germanium-metal configured Ge-photodetectors (MGM-PDs) under photovoltaic mode (i.e., 0-V operation). The metal contacts are engineered by an asymmetrical (i.e., boron and arsenic) dopant-segregation scheme on Schottky-contacts to suppress the dark current, and are with scaled spacing (∼0.8 μm). The MGM-PD (with ∼300-nm-thick Ge) is integrated on a silicon-on-isolator waveguide with complementary metal-oxide-semiconductor field effect transistor compatible process. For λ = 1550 nm, under 0-V bias, the devices illustrate a reasonable responsivity ∼0.17 A/W and a fast pulse response of 18 ps. © 2008 IEEE.Publication Evanescent-coupled Ge p-i-n photodetectors on Si-waveguide with SEG-Ge and comparative study of lateral and vertical p-i-n configurations(2008-05) Wang, J.; Loh, W.Y.; Chua, K.T.; Zang, H.; Xiong, Y.Z.; Loh, T.H.; Yu, M.B.; Lee, S.J.; Lo, G.-Q.; Kwong, D.-L.; ELECTRICAL & COMPUTER ENGINEERING; PHYSICSSi-waveguide-integrated lateral Ge p-i-n photodetectors using novel Si/ SiGe buffer and two-step Ge-process are demonstrated for the first time. Comparative analysis between lateral Ge p-i-n and vertical p-Si/i-Ge/ n-Ge p-i-n is made. Light is evanescently coupled from Si waveguide to the overlaying Ge-detector, achieving high responsivity of 1.16 A/W at 1550 nm with f3db bandwidth of 3.4 GHz for lateral Ge p-i-n detector at 5 V reverse bias. In contrast, vertical p-Si/i-Ge/n-Ge p-i-n has lower responsivity of 0.29 A/W but higher bandwidth of 5.5 GHz at 5 V bias. The higher responsivity of lateral p-i-n detectors is attributed to smaller optical mode overlap with highly doped Ge region as in vertical p-i-n configuration. © 2008 IEEE.Publication Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors(2008) Peng, J.W.; Lee, S.J.; Liang, G.C.A.; Singh, N.; Zhu, S.Y.; Lo, G.Q.; Kwong, D.L.; ELECTRICAL & COMPUTER ENGINEERINGThis letter presents the performance improvement of Schottky barrier metal-oxide-semiconductor field-effect transistor by employing gate-all-around (GAA) Si-nanowire (SiNW) structure. Without employing any barrier lowering technique, the mid-band-gap Ni-silicide Schottky barrier transistors demonstrated excellent performance and achieved subthreshold slope of ∼86 mV/decade and on-current of 19 μA/μm on a 12.5 nm SiNW, and subthreshold slope of ∼79 mV/decade and on-current of 207 μA/μm on a 4 nm diameter SiNW. Assisted with simulation, we show that this improvement can be attributed to the strong reduction in the Schottky barrier thickness as a result of the better gate control of GAA SiNW structure. © 2008 American Institute of Physics.Publication Dual Poly-Si Gate Metal Oxide Semiconductor Field Effect Transistors Fabricated with High-Quality Chemical Vapor Deposition HfO 2 Gate Dielectrics(2003-12) Lee, S.; Kwong, D.-L.; ELECTRICAL & COMPUTER ENGINEERINGIn this paper, we report the electrical characteristics of n- and p-metal oxide semiconductor field effect transistors (MOSFETs) fabricated using a high-quality ultrathin (equivalent oxide thickness ∼11 Å) chemical vapor deposition (CVD) HfO 2 gate stack with a selfaligned dual poly-Si gate process. The CVD HfO 2 gate stack exhibits excellent thermal stability with the poly-Si gate up to 1050°C, after 30 s annealing. Good output MOS characteristics with high drive current capability, excellent subthreshold swings, and good mobility are obtained from both n- and p-MOSFETs.Publication Germanium nanowire metal-oxide-semiconductor field-effect transistor fabricated by complementary-metal-oxide-semiconductor-compatible process(2011-01) Peng, J.W.; Singh, N.; Lo, G.Q.; Bosman, M.; Ng, C.M.; Lee, S.J.; ELECTRICAL & COMPUTER ENGINEERINGThis work presents a complementary metaloxidesemiconductor-compatible topdown fabrication of Ge nanowires along with their integration into pMOSFETs with "HfO2/TaN" high-k/metal gate stacks. Lateral Ge wires down to 14 nm in diameter are achieved using a two-step dry etch process on a high-quality epitaxial Ge layer. To improve the interface quality between the Ge nanowire and the HfO2, thermally grown GeO2 and epitaxial-Si shells are used as interlayers. Devices with a GeO2 shell demonstrated excellent ION/I OFF} ratios (>106), whereas the epitaxial-Si shell was found to improve the field-effect mobility of the holes in Ge nanowires to 254 cm2V -1.s-1. © 2010 IEEE.Publication New developments in Schottky source/drain high-k/metal gate CMOS transistors(2005) Li, M.-F.; Lee, S.; Zhu, S.; Li, R.; Chen, J.; Chin, A.; Kwong, D.L.; ELECTRICAL & COMPUTER ENGINEERINGRecent developments in Schottky source/drain high-k/metal gate CMOS transistors (SSDT) will be presented. Bulk SSDTs with 1.5-2 nm HfO2 (or HfAlO) gate dielectric and HfN/TaN metal gate have been fabricated using a novel low temperature process. The Si N-SSDT using YbSi2-x suicide, due to the lower Schottky electron barrier of YbSi2.x/Si, has demonstrated a record high Ion/Ioff ratio of ∼10 7 and a steep subthreshold slope of 75 mV/dec. For P-SSDT, the Si SSDT using PtSi silicide S/D shows excellent Ion/Ioff of ∼ 107-108 and subthreshold slope of ∼ 66 mV/dec, while the Ge SSDT using NiGe S/D shows Ion ∼ 5 times larger than that of the Si counterpart with PtSi S/D, due to the lower hole Schottky barrier and the higher hole mobility of Ge channel. The implant-free low temperature process relaxes the thermal budget of high-k dielectric and metal gate Fermi pinning. More improved performances are expected by using ultra-thin-body (UTB) SOI or GOI structures, showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.Publication Silicon nanowires thermoelectric devices(2010) Li, Y.; Buddharaju, K.; Singh, N.; Lo, G.Q.; Lee, S.J.; ELECTRICAL & COMPUTER ENGINEERINGThermoelectric units have been promising candidates at micro processor cooling and even at power generation at a micro-watt level. In fact thermoelectric energy converters can directly convert even low-grade heat gradients to electricity. However it has been a challenging task to scale down conventional thermoelectric materials as most of them are not CMOS compatible. Recent works on Silicon Nanowire arrays show great promise as highly scalable and efficient thermoelectric materials. In this work, we explore the potential of Silicon nanowires as a thermoelectric device. Numerical simulations on Silicon nanowires are performed to investigate both the power generation and cooling capability. Practical perspectives surrounding cover/insulation of wires cannot be avoided completely, hence in the cooling simulations, we included both the cooling potential of single isolated Silicon nanowire and Silicon nanowire with surrounding cover. Silicon nanowire individually has a large cooling power density but it was found that the inclusion of a surrounding material has a detrimental effect on the cooling performance. ©2010 IEEE.Publication CMOS compatible Ge/Si core/shell nanowire gate-all-around pMOSFET integrated with HfO2/TaN gate stack(2009) Peng, J.W.; Singh, N.; Lo, G.Q.; Kwong, D.L.; Lee, S.J.; ELECTRICAL & COMPUTER ENGINEERINGGe/Si core/shell gate-all-round nanowire pMOSFET integrated with HfO 2/TaN gate stack is demonstrated using fully CMOS compatible process. Devices with 100 nm gate length achieved high ION of ∼946 μA/μm at VG - VT = -0.7 V and VDS = -1 V and on/off ratio of 104 with decent subthreshold behavior. Significant improvement in hole mobility and ballistic efficiency is demonstrated as a result of core/shell channel architecture. © 2009 IEEE.Publication High germanium content strained SGOI by oxidation of amorphous SiGe film on SOI substrates(2005) Gao, F.; Balakumar, S.; Balasubramanian, N.; Lee, S.J.; Tung, C.H.; Kumar, R.; Sudhiranjan, T.; Foo, Y.L.; Kwong, D.-L.; ELECTRICAL & COMPUTER ENGINEERINGWe report the fabrication of single-crystalline Si0.4Ge 0.6-on-insulator by oxidizing cosputtered amorphous SiGe film on silicon-on-insulator (SOI) substrates. After a two-step oxidation process, thin SiGe0.6-on-insulator (SGOI) film with a uniform Ge concentration has been achieved. Various defects were observed during condensation. Crystalline properties of the SGOI layers are investigated by micro-Raman technique. The anisotropy of the strain in the Si0.4Ge0.6 film is deconvolved by high-resolution X-ray diffraction measurements and the estimated Ge content closely matches with energy dispersive X-ray analysis in cross-sectional transmission electron microscopy. The overall strain in these SGOI films is beneficial for the improvement of hole mobility of the metal-oxide-semiconductor field effect transistors. A cyclic annealing step is found to be effective for improving the film quality of Si0.4Ge 0.6-on-insulator. Such a cost-effective and simple method is promising for fabricating high Ge-content strained SiGe-on-insulator and pure Ge-on-insulator structures for high mobility device applications. © 2005 The Electrochemical Society. All rights reserved.Publication Characterization of sputtered TiO2 gate dielectric on aluminum oxynitride passivated p-GaAs(2008) Dalapati, G.K.; Sridhara, A.; Wong, A.S.W.; Chia, C.K.; Lee, S.J.; Chi, D.; ELECTRICAL & COMPUTER ENGINEERINGStructural and electrical characteristics of sputtered Ti O2 gate dielectric on p-GaAs substrates have been investigated. It has been demonstrated that the introduction of thin aluminum oxynitride (AlON) layer between Ti O2 and p-GaAs improves the interface quality. X-ray photoelectron spectroscopy and transmission electron microscopy results show that the AlON layer effectively suppresses the interfacial oxide formation during thermal treatment. The effective dielectric constant value is 1.5 times higher for the Ti O2 AlON gate stack compared to directly deposited Ti O2 on p-GaAs substrates, with a comparable interface state density. The capacitance-voltage (C-V), current-voltage (I-V) characteristics, and charge trapping behavior of the Ti O2 AlON gate stack under constant voltage stressing exhibit an excellent interface quality and high dielectric reliability, making the films suitable for GaAs based complementary metal-oxide-semiconductor technology. © 2008 American Institute of Physics.