Ma Htwe Htwe Hlaing
Email Address
elemhhh@nus.edu.sg
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Publication Thermally robust TaTbxN metal gate electrode for n-MOSFETs applications(2005-02) Ren, C.; Yu, H.Y.; Wang, X.P.; Ma, H.H.H.; Chan, D.S.H.; Li, M.-F.; Yeo, Y.-C.; Tung, C.H.; Balasubramanian, N.; Huan, A.C.H.; Pan, J.S.; Kwong, D.-L.; ELECTRICAL & COMPUTER ENGINEERINGIn this letter, we study Terbium (Tb)-incorporated TaN (TaTb xN) as a thermally robust N-type metal gate electrode for the first time. The work function of the Ta0.94Tb 0.06Ny metal gate is determined to be ∼ 4.23 eV after rapid thermal anneal at 1000 °C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb xN-SiO2 gate stack exhibits excellent thermal stability up to 1000 °C with no degradation to the equivalent oxide thickness, gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTbxN) could be a promising metal gate candidate for n-MOSFET in a dual-metal gate Si CMOS process. © 2005 IEEE.Publication Direct trim etching process of Si/SiO2 gate stacks using 193 nm ArF patterns(2004-07) Tan, K.M.; Yoo, W.J.; Ma, H.H.H.; Li, F.; Chan, L.; ELECTRICAL & COMPUTER ENGINEERINGA polysilicon gate of 30 nm length was fabricated by direct trimming of a gate stack using a 193 nm photoresist process and by trimming the polysilicon gate with HBr/Cl2 plasma chemistry in an inductively coupled plasma (ICP) etcher. HBr was found to be an effective trimming etchant due to its higher trimming rate. The inclusion of Sf6 and O2 to the plasma and the longer trimming time were found to effect the reduction in the polysilicon footprint effectively. The results show that the trimming rate increases with an increase in ICP power from 200 to 800 W and decreases with decreasing pressure.Publication Fermi pinning-induced thermal instability of metal-gate work functions(2004-05) Yu, H.Y.; Ren, C.; Yeo, Y.-C.; Kang, J.F.; Wang, X.P.; Ma, H.H.H.; Li, M.-F.; Chan, D.S.H.; Kwong, D.-L.; ELECTRICAL & COMPUTER ENGINEERINGThe dependence of the metal-gate work function on the annealing temperature is experimentally studied. We observe increased Fermi-level pinning of the metal-gate work function with increased annealing temperature. This effect is more significant for SiO2 than for HfO2 gate dielectric. A metal-dielectric interface model that takes the role of extrinsic states into account is proposed to explain the work function thermal instability. This letter provides new understanding on work function control for metal-gate transistors and on metal-dielectric interfaces.Publication A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate(2004-08) Ren, C.; Yu, H.Y.; Kang, J.F.; Wang, X.P.; Ma, H.H.H.; Yeo, Y.-C.; Chan, D.S.H.; Li, M.-F.; Kwong, D.-L.; ELECTRICAL & COMPUTER ENGINEERINGA novel replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide thickness (EOT) HfO2 gate dielectric is demonstrated. The excellent thermal stability of the HfN-HfO2 gate stack enables its use in high temperature CMOS processes. The replacement of HfN with other metal gate materials with work functions adequate for n- and pMOS is facilitated by a high etch selectivity of HfN with respect to HfO2, without any degradation to the EOT, gate leakage, or time-dependent dielectric breakdown characteristics of HfO2. By replacing the HfN dummy gate with Ta and Ni in nMOS and pMOS devices, respectively, a work function difference of ∼0.8 eV between nMOS and pMOS gate electrodes is achieved. This process could be applicable to sub-50-nm CMOS technology employing ultrathin HfO2 gate dielectric. © 2004 IEEE.Publication Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs(2006-01) Wang, X.P.; Li, M.-F.; Ren, C.; Yu, X.F.; Shen, C.; Ma, H.H.; Chin, A.; Zhu, C.X.; Ning, J.; Yu, M.B.; Kwong, D.-L.; ELECTRICAL & COMPUTER ENGINEERINGUsing a novel HfLaO gate dielectric for nMOSFETs with different La composition, we report for the first time that TaN (or HfN) effective metal gate work function can be tuned from Si mid-gap to the conduction band to fit the requirement of nMOSFETs. This is explained by the change of interface states and Fermi pinning level by adding La into HfO2. The superior performances of the nMOSFETs compared with those using pure HfO2 gate dielectric are also reported, in terms of higher crystallization temperature and higher drive current Id without sacrifice of very low gate leakage current, i.e. 5-6 orders reduction compared with SiO2 at the same equivalent oxide thickness of ∼1.2-1.8 nm. © 2005 IEEE.