Narayanan Balasubramanian
Email Address
elenb@nus.edu.sg
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Publication Transport characteristics of Si nanowires in bulk silicon and SOI wafers(2006) Agarwal, A.; Singh, N.; Liow, T.-Y.; Kumar, R.; Balasubramanian, N.; Kwong, D.L.; ELECTRICAL & COMPUTER ENGINEERINGSilicon nanowires (SiNW) were fabricated on bulk Silicon and SOI wafers by means of conventional Si process technology. The nanowires were formed by stress-limited oxidation of Si beams pre-patterned on the wafer. Single or double vertically self-aligned wires were obtained depending on the bulk or SOI wafer used and also on the depth of silicon beam etched. The resulting nanowires exhibit triangular cross-section that can be converted to circular shape by annealing at high temperatures, exploiting the visco-elastic properties of SiO2 and Si. Electrical measurements on single nanowire show that the resistance scales with length demonstrating consistent cross-sectional dimension in wires of different length. The nanowires formed on SOI wafers were also characterized as channels in FET configuration, using substrate as gate electrode. This technique can be exploited for realizing several nano-electronics, NEMS and biosensor applications in bulk silicon or SOI wafers, all in a CMOS compatible manner. © 2006 IEEE.Publication A partial SOI technology for single-chip RF power amplifiers(2001) Cai, J.; Ren, C.; Liang, Y.C.; Balasubramanian, N.; Sin, J.K.O.; ELECTRICAL & COMPUTER ENGINEERINGThe technology of forming partial SOI (silicon on insulator) platform on conventional bulk wafer is proposed. RF LDMOS devices with high power-added efficiency and on-chip high-Q value micro-inductors were fabricated for 2 GHz power amplifier applications by using the proposed technology. Devices were verified by the laboratory measurement results.Publication Wet etching characteristics and surface morphology evaluation of MOCVD grown HfO2 film(2004-09) Balasubramanian, M.; Bera, L.K.; Mathew, S.; Balasubramanian, N.; Lim, V.; Joo, M.S.; Cho, B.J.; ELECTRICAL & COMPUTER ENGINEERINGIn this work, we have investigated the wet etching of MOCVD grown HfO 2 film using diluted HF. The effect of various implant species on the etch rate was also extensively studied. Etch depth profile for as-deposited film shows that etch rate is higher at the surface and near the interface compared to its bulk. A ∼ 15 Å interfacial layer is unable to etch completely. The etch rate for annealed samples, prior to implant, is negligible due to crystallization. BF2, and As implanted samples after RTA show enhanced etching in DHF. The etch rate of As implanted samples are faster than BF2. However, B and P implanted samples shows negligible etch rate. Effect of implant species on surface roughness is not substantial. All samples show a RMS surface roughness (2-3 Å) after RTA. Etched samples show large surface roughness (max: 26 Å). © 2004 Published by Elsevier B.V.Publication Investigation of electrical properties of furnace grown gate oxide on strained-Si(2004-09) Bera, L.K.; Mathew, S.; Balasubramanian, N.; Leitz, C.; Braithwaite, G.; Singaporewala, F.; Yap, J.; Carlin, J.; Langdo, T.; Lochtefeld, T.; Currie, M.; Hammond, R.; Fiorenza, J.; Badawi, H.; Bulsara, M.; ELECTRICAL & COMPUTER ENGINEERINGEffect of strained-Si thickness on electrical properties of furnace grown gate oxide has been investigated. Interface state density (Dit) versus energy characteristics shows that Dit increases with decreasing strained-Si thickness, probably due to the presence of Ge at the interface. From conductance measurement, two different types of traps are observed in the gate oxide. In thinner strained-Si samples, the onset of F-N tunneling happens at higher voltages, indicating thicker gate oxide. Gate voltage oscillations were observed during constant current stress under gate injection at low stress current. This sinusoidal characteristics are possibly due to the trapping and detrapping of charges in the oxide. © 2004 Esevier B.V. All rights reserved.Publication Process for device using partial SOI(2003-04-22) JUN, CAI; HONG, REN CHANG; NAGARAJAN, RANGANATHAN; BALASUBRAMANIAN, NARAYANAN; LIANG, YUNG CHII; ELECTRICAL & COMPUTER ENGINEERING; MATERIALS SCIENCE; INSTITUTE OF MICROELECTRONICS (SINGAPORE, SG); NATIONAL UNIVERSITY OF SINGAPOREA process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of wade whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device.Publication Method of fabricating a CMOS device with dual metal gate electrodes(2008-01-08) PARK, CHANG SEO; CHO, BYUNG JIN; BALASUBRAMANIAN, NARAYANAN T.; ELECTRICAL & COMPUTER ENGINEERING; NATIONAL UNIVERSITY OF SINGAPOREA method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AIN.sub.x) buffer layer between the metal gate and gate dielectric during processing for preventing the gate dielectric from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer is completely consumed through reaction with the metal gate and a new metal alloy is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer and gate metals play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.Publication Si nanowire CMOS transistors and circuits by top-down technology approach(2008) Balasubramanian, N.; Singh, N.; Rustogi, S.C.; Buddharaju, K.D.; Fu, J.; Hui, Z.; Balakumar, S.; Agarwal, A.; Manhas, S.K.; Lo, G.Q.; Kwong, D.L.; ELECTRICAL & COMPUTER ENGINEERINGFor the end of the roadmap CMOS scaling, the non-classical device architecture, Gate All Around (GAA) FET with nanowire (NW) channel body offers the ultimate electro-static control and thus has the potential to push the gate length to few nanometers. The key challenge for NWs to be widely adopted in CMOS IC industry is that they have to be formed by large scale manufacturing methods and devoid of contamination issues. Top-down methods using lithography and etching suit CMOS applications in general and also provides a well-established CMOS based platform for creating devices for other applications. We have developed such a technology platform for Si NW fabrication with NW diameter down to 3 nm. This paper gives an overview of our technology approach, GAA Transistors, CMOS inverters, logic gates, ring oscillators, nanocrystal embedded SONOS memory devices and an introduction to high Ge content SiGe nanowires. © The Electrochemical Society.