Radhakrishnan, M K
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Publication Structural analysis of breakdown in ultrathin gate dielectrics using transmission electron microscopy(2004) Pey, K.L.; Tung, C.H.; Tang, L.J.; Ranjan, R.; Radhakrishnan, M.K.; Lin, W.H.; Lombardo, S.; Palumbo, F.; INSTITUTE OF MICROELECTRONICSTransmission electron microscopy (TEM) has been successfully applied to study the microstructural defects responsible for the breakdown in ultrathin SiO xN y and Si 3N 4, and HfO 2 gate dielectrics. Contradicting to the general belief that gate oxide defects are confined within the gate dielectrics, the TEM analysis reveals that the physical defects associated with the gate dielectric breakdown involve both the gate electrodes i.e., poly-Si gate and Si substrate. High resolution TEM and chemical/elemental analysis in TEM show that regrowth of Si epitaxy, gate dielectric thinning, suicide migration, poly-Si gate melt-down and recrystallization, Si substrate point defects and metallization/contact burnt-out are common gate dielectric breakdown induced failure defects, and their presence depends strongly on the growth of the hardness of the breakdown. In this paper, we present a detailed TEM analysis on the main microstructural defects responsible for the breakdown of ultrathin gate dielectrics. © 2004 IEEE.Publication Gate Dielectric-Breakdown-Induced Microstructural Damage in MOSFETs(2004-03) Tang, L.J.; Pey, K.L.; Tung, C.H.; Radhakrishnan, M.K.; Lin, W.H.; INSTITUTE OF MICROELECTRONICSNumerous failure mechanisms associated with hard breakdowns (HBD) in ultrathin gate oxides were physically studied with high-resolution transmission electron microscope (TEM). Migration of silicide from silicided gate and source/drain regions, abnormal growth of dielectric-breakdown-induced epitaxy (DBIE), poly-Si gate meltdown and recrystallization, severe damage in Si substrate, and total epitaxy of poly-Si gate and Si substrate of the entire transistor are among the common microstructural damages observed in metal-oxide-semiconductor field-effect transistors (MOSFETs) after HBDs in gate oxides (Gox) were observed electrically. The type of catastrophic failures and its degree of damage were found to be strongly dependent on the allowable current density and total resistance of the breakdown path during the breakdown transient. The physical analysis data from TEM analysis allow us to establish the sequence of the physical damage associated with the Gox HBD in narrow transistors. The proposed model is able to predict the next possible microstructural damage induced by HBD. Stich knowledge will allow failure analysts to be able to retro-predict the current and power consumption in a field EOS/ESD failure based on the physical analysis and propose a knowledgeable guess on the potential root cause of the failures.Publication Gate dielectric degradation mechanism associated with DBIE evolution(2004) Pey, K.L.; Ranjan, R.; Tung, C.H.; Tang, L.J.; Lin, W.H.; Radhakrishnan, M.K.; INSTITUTE OF MICROELECTRONICSThe degradation mechanism of breakdown spots in ultrathin gate dielectrics metal-oxide-semiconductor transistor associated with dielectric-breakdown- induced epitaxy (DBIE) evolution is physically analyzed using high resolution transmission electron microscope (HRTEM). The initial soft breakdown location triggered by percolation path happens randomly along the transistor channel, and then evolves to the formation of DBIE in the vicinity of the percolation path. If the breakdown leakage current is not limited, DBIE will grow and the effective breakdown location will successively shift to either source or drain of the transistor channel. For most of the hard breakdown events studied, DBIE eventually shorts the gate electrode to either source or drain region, leading to a typical one-sided hard breakdown seen electrically, which confirms by HRTEM images.Publication Geometry dependence of gate oxide breakdown evolution(2004) Sun, Y.; Pey, K.L.; Tung, C.H.; Lombardo, S.; Palumbo, F.; Tang, L.J.; Radhakrishnan, M.K.; INSTITUTE OF MICROELECTRONICSThe effects of geometrical arrangement of MOSFETs on breakdown (BD) evolution in ultrathin gate oxide have been studied. Specific attention was paid to the impact of heat confinement in narrow MOSFETs on the BD evolution from soft BD to hard BD. It is found that based on a numerical simulation, the thermal effect, which is the main driving force of catastrophic BD, is more severe in narrow MOSFETs than wide MOSFETs, which is in agreement with the degradation rate measured from their respective BD transients. © 2004 IEEE.Publication A new breakdown failure mechanism in HfO 2 gate dielectric(2004) Ranjan, R.; Pey, K.L.; Tang, L.J.; Tung, C.H.; Groeseneken, G.; Radhakrishnan, M.K.; Kaczer, B.; Degraeve, R.; De Gendt, S.; INSTITUTE OF MICROELECTRONICSThe breakdown failure mechanism in HfO 2 high-k gate dielectrics under constant voltage stress in inversion and accumulation mode is physically analyzed with the aid of high resolution transmission electron microscopy. The results show that the breakdown phenomenon in HfO 2 gate dielectrics is different from that of ultrathin SiO xN y and Si 3N 4 gate dielectrics. Dielectricbreakdown-induced epitaxy, which is the failure defect responsible for breakdown in SiO xN y and Si 3N 4 has also been observed in HfO 2 but in a slightly different morphology. The microstructural damages observed in the breakdown of HfO 2 gate dielectrics are probably related to HfSi x and HfSiO x formation during BD event.Publication Size difference in dielectric-breakdown-induced epitaxy in narrow n- and p-metal oxide semiconductor field effect transistors(2003-10-06) Pey, K.L.; Tung, C.H.; Tang, L.J.; Lin, W.H.; Radhakrishnan, M.K.; INSTITUTE OF MICROELECTRONICSSize-difference in dielectric-breakdown-induced epitaxy in narrow n- and p-metal oxide semiconductor field effect transistors (MOSFET) was discussed. It was found that physical dimensions formed during gate-dielectrics-breakdown-induced epitaxy (DBIE) is dependent on transistor type. Results also showed that DBIE in n-MOSFET are almost 2 times larger than in the p-MOSFET.Publication Expanded Papers From the 2003 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)(2004-03) Pey, K.L.; Radhakrishnan, M.K.; Trigg, A.; INSTITUTE OF MICROELECTRONICSPublication Structure of the breakdown spot during progressive breakdown of ultra-thin gate oxides(2004) Palumbo, F.; Lombardo, S.; Pey, K.L.; Tang, L.J.; Tung, C.H.; Lin, W.H.; Radhakrishnan, M.K.; Falci, G.; INSTITUTE OF MICROELECTRONICSThe structure of the breakdown spot during progressive breakdown (BD) of ultra-thin gate oxide was studied. The nMOSFETs were stressed at +4V. To study the physical structure of the BD spot during progressive BD, it is important to perform the analysis on small geometry devices, to facilitate the TEM analysis. It was shown that the progressive BD is the dominant BD mode under conditions in CMOS circuits. The MOSFET devices were subjected to accelerated stresses at constant voltage in inversion at room temperature.Publication Die attach failures related to wafer back metal processing - An AES study(1997-03) Radhakrishnan, M.K.; INSTITUTE OF MICROELECTRONICSDie attach failures on Cr/Ni/Au back-metallised silicon wafers have been studied under different process conditions. The Auger studies on the failed devices show that the formation of nickel oxide causes poor die attachment even for an Au film thickness of ∼ 500 Å. The failures simulated experimentally revealed that nickel oxide formation depends on the film sintering conditions. Cppyright © 1996 Elsevier Science Ltd.Publication Device reliability and failure mechanisms related to gate dielectrics and interconnects(2004) Radhakrishnan, M.K.; INSTITUTE OF MICROELECTRONICSAs dimensions shrink, the reliability considerations become more trivial. In deep sub-micron devices, at certain stages of processing, even an atomic layer variation can be a defect. Studies on the physical failure mechanisms in sub-micron devices reveals that the major reliability concerns are the same as that poses before scaling. A comprehensive overview on the reliability issues in ultra thin gate dielectrics and copper interconnect material is given to link how the physical effects on devices can be a threat to long-term reliability.