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Yee Chia Yeo

rp09882

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Full Name
Yee Chia Yeo
Variants
Yeo, Y.
Yeo Y.-C.
Yeo, Y.C.
Yeo, Y.-C.
Yeo., Y.-C.
 
Main Affiliation
 
Faculty
 
Email
eleyeoyc@nus.edu.sg
 

Publications

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Date Issued:  [2000 TO 2009]

Results 1-20 of 226 (Search time: 0.004 seconds).

Issue DateTitleAuthor(s)
120085 nm gate length nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation techniqueLiow, T.-Y.; Tan, K.-M.; Lee, R.T.P. ; Zhu, M. ; Tan, B.L.-H.; Samudra, G.S. ; Balasubramanian, N.; Yeo, Y.-C. 
2200650 nm silicon-on-insulator N-MOSFET featuring multiple stressors: Silicon-carbon source/drain regions and tensile stress silicon nitride linerAng, K.-W.; Chui, K.-J.; Chin, H.-C.; Foo, Y.-L.; Du, A.; Deng, W.; Li, M.-F. ; Samudra, G. ; Balasubramanian, N.; Yeo, Y.-C. 
32008A complementary-I-MOS technology featuring SiGe channel and I-region for enhancement of impact-ionization, breakdown voltage, and performanceToh, E.-H.; Wang, G.H.; Chan, L.; Lo, G.-Q.; Sylvester, D.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
4Feb-2008A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performanceToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
5Aug-2004A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gateRen, C.; Yu, H.Y. ; Kang, J.F.; Wang, X.P.; Ma, H.H.H. ; Yeo, Y.-C. ; Chan, D.S.H. ; Li, M.-F. ; Kwong, D.-L.
6Jan-2006A fast measurement technique of MOSFET Id-Vg characteristicsShen, C.; Li, M.-F. ; Wang, X.P.; Yeo, Y.-C. ; Kwong, D.-L.
7Feb-2008A high-stress liner comprising diamond-like carbon (DLC) for strained p-channel MOSFETTan, K.-M.; Zhu, M. ; Fang, W.-W.; Yang, M.; Liow, T.-Y.; Lee, R.T.P. ; Hoe, K.M.; Tung, C.-H.; Balasubramanian, N.; Samudra, G.S. ; Yeo, Y.-C. 
82007A new liner stressor with very high intrinsic stress (> 6 GPa) and low permittivity comprising diamond-like carbon (DLC) for strained p-channel transistorsTan, K.-M.; Zhu, M. ; Fang, W.-W.; Yang, M.; Liow, T.-Y.; Lee, R.T.P. ; Hoe, K.M.; Tung, C.-H.; Balasubramanian, N.; Samudra, G.S. ; Yeo, Y.-C. 
92009A new robust non-local algorithm for band-to-band tunneling simulation and its application to tunnel-FETShen, C.; Yang, L.T.; Toh, E.-H.; Heng, C.-H. ; Samudra, G.S. ; Yeo, Y.-C. 
102008A new salicidation process with solid Antimony (Sb) segregation (SSbS) for achieving sub-0.1 eV effective schottky barrier height and parasitic series resistance reduction in N-channel transistorsWong, H.-S.; Koh, A.T.-Y.; Chin, H.-C.; Lee, R.T.-P. ; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
112008A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel aAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stackChin, H.-C.; Zhu, M. ; Lee, Z.-C.; Liu, X.; Tan, K.-M.; Lee, H.K.; Shi, L. ; Tang, L.-J.; Tung, C.-H. ; Lo, G.-Q.; Tan, L.-S. ; Yeo, Y.-C. 
122008A new source/drain germanium-enrichment process comprising Ge deposition and laser-induced local melting and recrystallization for P-FET performance enhancementLiu, F.; Wong, H.-S.; Ang, K.-W.; Zhu, M. ; Wang, X.; Lai, D.M.-Y.; Lim, P.-C.; Tan, B.L.H.; Tripathy, S.; Oh, S.-A.; Samudra, G.S. ; Balasubramanian, N.; Yeo, Y.-C. 
132005A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistorToh, E.-H.; Wang, G.H.; Lo, G.-Q.; Balasubramanian, N.; Tung, C.-H.; Benistant, F.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
142007A strained N-channel impact-ionization MOS (I-MOS) transistor with elevated silicon-carbon source/drain for performance enhancementToh, E.-H.; Wang, G.H.; Lo, G.-Q.; Choy, S.-F.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
152008A variational approach to the two-dimensional nonlinear Poisson's equation for the modeling of tunneling transistorsShen, C.; Ong, S.-L.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
16Apr-2008Achieving conduction band-edge Schottky barrier height for arsenic-segregated nickel aluminide disilicide and implementation in FinFETs with ultra-narrow fin widthsLee, R.T.-P. ; Liow, T.-Y.; Tan, K.-M.; Lim, A.E.-J.; Koh, A.T.-Y.; Zhu, M. ; Lo, G.-Q.; Samudra, G.S. ; Chi, D.Z.; Yeo, Y.-C. 
172009Achieving sub-0.1 ev hole schottky barrier height for NiSiGe on SiGe by aluminum segregationSinha, M.; Lee, R.T.P. ; Lohani, A.; Mhaisalkar, S.; Chor, E.F. ; Yeo, Y.-C. 
182009Advanced contact technology for MOSFETs: Integration of new materials for series resistance reductionYeo, Y.-C. ; Lee, R.T.-P. 
192006Aluminum oxynitride interfacial passivation layer for high-permittivity gate dielectric stack on gallium arsenideZhu, M. ; Tung, C.-H.; Yeo, Y.-C. 
20May-2008Analysis of the effects of fringing electric field on finFET device performance and structural optimization using 3-D simulationZhao, H.; Yeo, Y.-C. ; Rustagi, S.C.; Samudra, G.S.