Browsing by Author Sin, J.K.O.

Showing results 1 to 13 of 13
Issue DateTitleAuthor(s)
Oct-2000120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limitXu, S.; Gan, K.P.; Samudra, G.S. ; Liang, Y.C.; Sin, J.K.O.
Dec-2005A new polysilicon CMOS self-aligned double-gate TFT technologyXiong, Z.; Liu, H.; Zhu, C. ; Sin, J.K.O.
Apr-2004A novel self-aligned offset-gated polysilicon TFT using high-κ dielectric spacersXiong, Z.; Liu, H.; Zhu, C. ; Sin, J.K.O.
2004A novel surface passivation process for HfO 2 Ge MOSFETsWu, N.; Zhang, Q.; Zhu, C. ; Chan, D.S.H. ; Li, M.F. ; Balasubramanian, N.; Du, A.Y.; Chin, A.; Sin, J.K.O.; Kwong, D.-L.
2001A partial SOI technology for single-chip RF power amplifiersCai, J.; Ren, C.; Liang, Y.C. ; Balasubramanian, N. ; Sin, J.K.O.
2005A simple CMOS self-aligned double-gate poly-Si TFT technologyXiong, Z.; Liu, H.; Zhu, C. ; Sin, J.K.O.
Sep-2004A TaN-HfO2-Ge pMOSFET with novel SiH4 surface passivationWu, N.; Zhang, Q.; Zhu, C. ; Chan, D.S.H. ; Du, A.; Balasubramanian, N.; Li, M.F. ; Chin, A.; Sin, J.K.O.; Kwong, D.-L.
Aug-2004Characteristics of high-κ spacer offset-gated polysilicon TFTsXiong, Z.; Liu, H.; Zhu, C. ; Sin, J.K.O.
Dec-2001Folded gate LDMOS transistor with low on-resistance and high transconductanceZhu, Y.; Liang, Y.C. ; Xu, S.; Foo, P.-D.; Sin, J.K.O.
2000Folded gate LDMOS with low on-resistance and high transconductanceXu, S.; Zhu, Y.; Foo, P.-D. ; Liang, Y.C. ; Sin, J.K.O.
2000Folded gate LDMOS with low on-resistance and high transconductanceXu, S.; Zhu, Y.; Foo, P.-D. ; Liang, Y.C. ; Sin, J.K.O.
Dec-2002The partial silicon-on-insulator technology for RF power LDMOSFET devices and on-chip microinductorsRen, C.; Cai, J.; Liang, Y.C. ; Ong, P.H.; Balasubramanian, N.; Sin, J.K.O.
Sep-2001Theoretical analysis and experimental characterization of the dummy-gated VDMOSFETXu, S.; Ren, C.; Liang, Y.C. ; Foo, P.-D.; Sin, J.K.O.