Browsing by Author Lo, G.-Q.

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Issue DateTitleAuthor(s)
2008A complementary-I-MOS technology featuring SiGe channel and I-region for enhancement of impact-ionization, breakdown voltage, and performanceToh, E.-H.; Wang, G.H.; Chan, L.; Lo, G.-Q.; Sylvester, D.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
2011A lens holder in conjunction with a MEMS platform for on-chip aligning and fixing of a ball lens in silicon photonics packagingZhang, Q.X.; Du, Y. ; Tan, C.W.; Zhang, J.; Yu, M.B.; Lo, G.-Q.; Kwong, D.-L.
2008A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel aAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stackChin, H.-C.; Zhu, M. ; Lee, Z.-C.; Liu, X.; Tan, K.-M.; Lee, H.K.; Shi, L. ; Tang, L.-J.; Tung, C.-H. ; Lo, G.-Q.; Tan, L.-S. ; Yeo, Y.-C. 
2005A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistorToh, E.-H.; Wang, G.H.; Lo, G.-Q.; Balasubramanian, N.; Tung, C.-H.; Benistant, F.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
Jan-2010A silicon platform with MEMS active alignment function and its potential application in Si-photonics packagingZhang, Q.X.; Du, Y. ; Tan, C.W.; Zhang, J.; Yu, M.B.; Yeoh, W.G.; Lo, G.-Q.; Kwong, D.-L.
2007A strained N-channel impact-ionization MOS (I-MOS) transistor with elevated silicon-carbon source/drain for performance enhancementToh, E.-H.; Wang, G.H.; Lo, G.-Q.; Choy, S.-F.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
Apr-2008Achieving conduction band-edge Schottky barrier height for arsenic-segregated nickel aluminide disilicide and implementation in FinFETs with ultra-narrow fin widthsLee, R.T.-P. ; Liow, T.-Y.; Tan, K.-M.; Lim, A.E.-J.; Koh, A.T.-Y.; Zhu, M. ; Lo, G.-Q.; Samudra, G.S. ; Chi, D.Z.; Yeo, Y.-C. 
2013Analytical modelling of high temperature characteristics on the DC responses for Schottky-gate AlGaN/GaN HEMT devicesWang, Y.-H.; Liang, Y.C. ; Samudra, G.S. ; Chang, T.-F.; Huang, C.-F.; Yuan, L.; Lo, G.-Q.
2009Characterization and modeling of subfemtofarad nanowire capacitance using the CBCM techniqueZhao, H.; Kim, R.; Paul, A.; Luisier, M.; Klimeck, G.; Ma, F.-J. ; Rustagi, S.C.; Samudra, G.S. ; Singh, N.; Lo, G.-Q.; Kwong, D.-L.
May-2008Evanescent-coupled Ge p-i-n photodetectors on Si-waveguide with SEG-Ge and comparative study of lateral and vertical p-i-n configurationsWang, J. ; Loh, W.Y.; Chua, K.T.; Zang, H.; Xiong, Y.Z.; Loh, T.H.; Yu, M.B.; Lee, S.J. ; Lo, G.-Q.; Kwong, D.-L.
2007Fabrication of strain relaxed silicon-germanium-on-insulator (Si 0.35Ge0.65OI) wafers using cyclical thermal oxidation and annealingWang, G.H.; Toh, E.-H.; Tung, C.-H.; Foo, Y.-L.; Tripathy, S.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
2009Gate-all-around quantum-wire field-effect transistor with dopant segregation at metal-semiconductor-metal heterostuctureWong, H.-S.; Tan, L.-H.; Chan, L.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
1-Dec-2008High-speed metal-germanium-metal configured PIN-like Ge-photodetector under photovoltaic mode and with dopant-segregated Schottky-contact engineeringZang, H.; Lee, S. ; Yu, M.; Loh, W.Y.; Wang, J. ; Lo, G.-Q.; Kwong, D.-L.
Dec-2006I-MOS transistor with an elevated silicon-germanium impact-ionization region for bandgap engineeringToh, E.-H.; Wang, G.H.; Chan, L.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
2007Impact ionization nanowire transistor with multiple-gates, silicon-germanium impact ionization region, and sub-5 mV/decade subtheshold swingToh, E.-H.; Wang, G.H.; Zhu, M. ; Shen, C.; Chan, L.; Lo, G.-Q.; Tung, C.-H.; Sylvester, D.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
2009Impacts of size and cross-sectional shape on surface lattice constant and electron effective mass of silicon nanowiresYao, D.; Zhang, G.; Lo, G.-Q.; Li, B. 
2009Integration of Al segregated NiSiGe/SiGe source/drain contact technology in p-FinFETs for drive current enhancementSinha, M.; Lee, R.T.P. ; Devi, S.N.; Lo, G.-Q.; Chor, E.F. ; Yeo, Y.-C. 
2009Integration of high-κ dielectrics and metal gate on gate-all-around si-nanowire-based architecture for high-speed nonvolatile charge-trapping memoryFu, J.; Singh, N.; Zhu, C. ; Lo, G.-Q.; Kwong, D.-L.
Jan-2010Low thermal budget monolithic integration of evanescent-coupled Ge-on-SOI photodetector on Si CMOS platformAng, K.-W.; Liow, T.-Y.; Yu, M.-B.; Fang, Q.; Song, J.; Lo, G.-Q.; Kwong, D.-L. 
Jul-2010Modeling of stress-retarded thermal oxidation of nonplanar silicon structures for realization of nanoscale devicesMa, F.-J. ; Rustagi, S.C.; Samudra, G.S. ; Zhao, H.; Singh, N.; Lo, G.-Q.; Kwong, D.-L.