Browsing by Author CHAN, LAP

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Issue DateTitleAuthor(s)
26-Jun-2001Embedded polysilicon gate MOSFETCHAN, LAP; CHA, CHER LIANG; CHOR, ENG FONG ; HAO, GONG ; LEE, TECK KOON
26-Jun-2001Formation of air gap structures for inter-metal dielectric applicationSOO, CHOI PHENG; TEE, KHENG CHOK; ONG, KOK KENG; CHAN, LAP
20-May-2003Incorporation of dielectric layer onto SThM tips for direct thermal analysisHU, CHANG CHAUN; PEY, KIN LEONG ; CHONG, YUNG FU; KIN, CHIM WAI ; NEUZIL, PAVEL; CHAN, LAP
16-May-2000Method and apparatus to image metallic patches embedded in a non-metal surfaceCHA, CHER LIANG RANDALL; GONG, HAO ; CHOR, ENG FONG ; CHAN, LAP
8-Nov-2011Method for fabricating semiconductor devices with reduced junction diffusionCOLOMBEAU, BENJAMIN; YEONG, SAI HOOI; BENISTANT, FRANCIS; INDAJANG, BANGUN; CHAN, LAP
15-Feb-2011Method for forming a shallow junction region using defect engineering and laser annealingONG, KUANG KIAN; YEONG, SAI HOOI; PEY, KIN LEONG ; CHAN, LAP; CHONG, YUNG FU
4-Dec-2001Method for forming self-aligned elevated transistorCHAN, LAP; CHA, CHER LIANG
26-Jun-2001Method to deposit a platinum seed layer for use in selective copper platingZHOU, MEI SHENG ; XU, GUO-QIN ; CHAN, LAP
24-Apr-2001Method to enhance global planarization of silicon oxide surface for IC device fabricationSOO, CHOI PHENG; CHAN, LAP
30-Jan-2001Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide processPEY, KIN-LEONG ; HO, CHAW SING; CHAN, LAP
18-Apr-2000Method to fabricate a large planar area ONO interpoly dielectric in flash deviceCHAN, LAP; CHA, CHER LIANG
12-Sep-2006Method to fabricate horizontal air columns underneath metal inductorCHAN, LAP; CHEW, KOK WAI JOHNNY; CHA, CHER LIANG; CHUA, CHEE TEE
11-Aug-2009Method to fabricate horizontal air columns underneath metal inductorCHAN, LAP; CHEW, KOK WAI JOHNNY; CHA, CHER LIANG; CHUA, CHEE TEE
27-Mar-2001Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishingCHAN, LAP; CHA, CHER LIANG; LEE, TECK KOON
2-Oct-2001Method to form shallow junction transistors while eliminating shorts due to junction spikingCHAN, LAP; CHA, CHER LIANG; SUNDARESAN, RAVISHANKAR
1-May-2001Method to form shallow trench isolation structures for borderless contacts in an integrated circuitGOH, KENNY HUA KOOI; CHAN, LAP; YAP, KOK SIONG 
28-Aug-2001Method to form uniform silicide featuresCHAN, LAP; HO, CHAW SING; LI, FONG YAU SAM ; NG, HOU TEE 
4-Sep-2001Method to reduce compressive stress in the silicon substrate during silicidationCHA, RANDALL CHER LIANG; CHUA, CHEE TEE; PEY, KIN LEONG ; CHAN, LAP
22-Oct-2002Passivation of copper interconnect surfaces with a passivating metal layerCHAN, LAP; YAP, KUAN PEI; TEE, KHENG CHOK; IP, FLORA S.; LOH, WYE BOON
8-Aug-2000Passivation of copper interconnect surfaces with a passivating metal layerCHAN, LAP; YAP, KUAN PEI; TEE, KHENG CHOK; IP, FLORA S.; LOH, WYE BOON