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DONG JIN SONG
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Issue Date
Title
Author(s)
2014
Learning assumptions for compositionalverification of timed systems
Lin, S.-W.
;
Andre, E.
;
Liu, Y.
;
Sun, J.
;
Dong, J.S.
2007
Machine-assisted proof support for validation beyond Simulink
Chen, C.
;
Dong, J.S.
;
Sun, J.
2010
Message from the General Chair
Dong, J.S.
2010
Mild dementia care at home - Integrating activity monitoring, user interface plasticity and scenario verification
Biswas, J.
;
Mokhtari, M.
;
Dong, J.S.
;
Yap, P.
2014
Model checking approach to automated planning
Li, Y.
;
Dong, J.S.
;
Sun, J.
;
Liu, Y.
;
Sun, J.
2008
Model checking CSP revisited: Introducing a process analysis toolkit
Sun, J.
;
Liu, Y.
;
Dong, J.S.
2005
Model checking live sequence charts
Sun, J.
;
Dong, J.S.
2012
Model checking software architecture design
Zhang, J.
;
Liu, Y.
;
Sun, J.
;
Dong, J.S.
;
Sun, J.
Feb-2014
Model checking with fairness assumptions using PAT
Si, Y.
;
Sun, J.
;
Liu, Y.
;
Dong, J.S.
;
Pang, J.
;
Zhang, S.J.
;
Yang, X.
2010
Model-based methods for linking Web service choreography and orchestration
Sun, J.
;
Liu, Y.
;
Dong, J.S.
;
Pu, G.
;
Tan, T.H.
2006
Modeling and customization of fault tolerant architecture using object-Z/XVCL
Ling, Y.
;
Jin, S.D.
;
Jing, S.
2013
Modeling and verifying hierarchical real-time systems using stateful timed CSP
Sun, J.
;
Liu, Y.
;
Dong, J.S.
;
Shi, L.
;
André, E.
2012
More anti-chain based refinement checking
Wang, T.
;
Song, S.
;
Sun, J.
;
Liu, Y.
;
Dong, J.S.
;
Wang, X.
;
Li, S.
2011
On combining state space reductions with global fairness assumptions
Zhang, S.J.
;
Sun, J.
;
Pang, J.
;
Liu, Y.
;
Dong, J.S.
2008
Ontology generation through the fusion of partial reuse and relation extraction
Tun, N.N.
;
Dong, J.S.
2012
Parameter synthesis for hierarchical concurrent real-time systems
Andre, E.
;
Liu, Y.
;
Sun, J.
;
Dong, J.-S.
2011
PAT 3: An extensible architecture for building multi-domain model checkers
Liu, Y.
;
Sun, J.
;
Dong, J.S.
2009
PAT: Towards flexible verification under fairness
Sun, J.
;
Liu, Y.
;
Dong, J.S.
;
Pang, J.
2012
Planning as model checking tasks
Li, Y.
;
Sun, J.
;
Dong, J.S.
;
Liu, Y.
;
Sun, J.
2010
Preface of the 2010 IAENG International Conference on Electrical Engineering special session: Design, analysis and tools for integrated circuits and systems
Man, K.L.
;
Mercaldi, M.
;
Hahanov, V.
;
Prinetto, P.
;
Poncino, M.
;
MacIi, A.
;
Choi, J.
;
Li, W.
;
Schellekens, M.
;
Popovici, E.
;
Seon, J.-K.
;
Rossi, U.
;
Fummi, F.
;
Pravadelli, G.
;
Lam, Y.F.
;
PavLov, V.
;
Patel, A.
;
Huang, J.
;
Vallee, T.
;
Boubekeur, M.
;
Sokolova, A.
;
Almerares, S.
;
Donno, M.
;
Cho, J.-D.
;
Zahirul Alam, A.H.M.
;
Provan, G.
;
Velev, M.N.
;
Uddin, M.N.
;
Botchkarev, A.
;
Bosnacki, D.
;
Hickey, D.
;
O'Keeffe, M.
;
Krilavičius, T.
;
Pastrnak, M.
;
Herbert, J.
;
Lu, Z.-M.
;
Pan, J.-S.
;
Chang, C.-C.
;
Horng, M.-F.
;
Chen, L.
;
Lim, C.-P.
;
Tao, N.Q.
;
Deb, S.
;
Merniz, S.
;
Valero, O.
;
Yi, Y.
;
Woods, D.
;
Vedrine, F.
;
Monsuez, B.
;
Yen, K.
;
Matsuura, T.
;
Edwards, R.T.
;
Tveretina, O.
;
Fino, M.H.
;
O'Riordan, A.P.
;
Labiak, G.
;
Gaur, M.S.
;
Chang, J.
;
Chung, Y.-C.
;
Derezinska, A.
;
Cho, K.-R.
;
Zhang, Y.
;
Liutkevičius, R.
;
Zeng, Y.
;
Vasudevan, D.P.
;
Bukowiec, A.
;
Kitsos, P.
;
Goudarzi, M.
;
Dong, J.S.
;
Bhalla, A.
;
Al-Khalili, D.
;
Navabi, Z.
;
Zinchenko, L.
;
Anjum, M.A.
;
Narasimha, D.L.
;
Hughes, D.
;
Tadjouddine, E.M.
;
Wang, J.
;
Kumar, A.P.S.
;
Jaisankar, N.
;
Mansoor, A.
;
Hollands, S.
;
Mohammadi, S.
;
Klein, F.
;
Westermann, P.
;
English, T.
;
Planas, M.M.
;
Chung, C.
;
Chakrabarti, A.
;
Lei, C.-U.
;
Bamakhrama, M.
;
Naik, B.R.
;
Harte, S.
;
Yin, A.
;
Giancardi, L.
;
El-Din Mady, A.
;
Joseph, A.
;
Khandekar, P.D.
;
Pandey, H.M.
;
Bharti, V.
;
O'Mullane, M.
;
Chen, C.