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Browsing by Author DONG JIN SONG

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Showing results 65 to 84 of 127 < previous   next >
Issue DateTitleAuthor(s)
2014Learning assumptions for compositionalverification of timed systemsLin, S.-W. ; Andre, E.; Liu, Y.; Sun, J.; Dong, J.S. 
2007Machine-assisted proof support for validation beyond SimulinkChen, C. ; Dong, J.S. ; Sun, J. 
2010Message from the General ChairDong, J.S. 
2010Mild dementia care at home - Integrating activity monitoring, user interface plasticity and scenario verificationBiswas, J.; Mokhtari, M.; Dong, J.S. ; Yap, P.
2014Model checking approach to automated planningLi, Y.; Dong, J.S. ; Sun, J.; Liu, Y.; Sun, J.
2008Model checking CSP revisited: Introducing a process analysis toolkitSun, J. ; Liu, Y. ; Dong, J.S. 
2005Model checking live sequence chartsSun, J. ; Dong, J.S. 
2012Model checking software architecture designZhang, J.; Liu, Y.; Sun, J.; Dong, J.S. ; Sun, J.
Feb-2014Model checking with fairness assumptions using PATSi, Y.; Sun, J.; Liu, Y.; Dong, J.S. ; Pang, J.; Zhang, S.J.; Yang, X.
2010Model-based methods for linking Web service choreography and orchestrationSun, J.; Liu, Y. ; Dong, J.S. ; Pu, G.; Tan, T.H.
2006Modeling and customization of fault tolerant architecture using object-Z/XVCLLing, Y.; Jin, S.D. ; Jing, S.
2013Modeling and verifying hierarchical real-time systems using stateful timed CSPSun, J.; Liu, Y.; Dong, J.S. ; Shi, L.; André, E. 
2012More anti-chain based refinement checkingWang, T.; Song, S.; Sun, J.; Liu, Y. ; Dong, J.S. ; Wang, X.; Li, S.
2011On combining state space reductions with global fairness assumptionsZhang, S.J.; Sun, J.; Pang, J.; Liu, Y. ; Dong, J.S. 
2008Ontology generation through the fusion of partial reuse and relation extractionTun, N.N. ; Dong, J.S. 
2012Parameter synthesis for hierarchical concurrent real-time systemsAndre, E.; Liu, Y. ; Sun, J.; Dong, J.-S. 
2011PAT 3: An extensible architecture for building multi-domain model checkersLiu, Y. ; Sun, J.; Dong, J.S. 
2009PAT: Towards flexible verification under fairnessSun, J. ; Liu, Y. ; Dong, J.S. ; Pang, J.
2012Planning as model checking tasksLi, Y.; Sun, J.; Dong, J.S. ; Liu, Y. ; Sun, J.
2010Preface of the 2010 IAENG International Conference on Electrical Engineering special session: Design, analysis and tools for integrated circuits and systemsMan, K.L.; Mercaldi, M.; Hahanov, V.; Prinetto, P.; Poncino, M.; MacIi, A.; Choi, J.; Li, W.; Schellekens, M.; Popovici, E.; Seon, J.-K.; Rossi, U.; Fummi, F.; Pravadelli, G.; Lam, Y.F.; PavLov, V.; Patel, A.; Huang, J.; Vallee, T.; Boubekeur, M.; Sokolova, A.; Almerares, S.; Donno, M.; Cho, J.-D.; Zahirul Alam, A.H.M.; Provan, G.; Velev, M.N.; Uddin, M.N.; Botchkarev, A.; Bosnacki, D.; Hickey, D.; O'Keeffe, M.; Krilavičius, T.; Pastrnak, M.; Herbert, J.; Lu, Z.-M.; Pan, J.-S.; Chang, C.-C.; Horng, M.-F.; Chen, L.; Lim, C.-P.; Tao, N.Q.; Deb, S.; Merniz, S.; Valero, O.; Yi, Y.; Woods, D.; Vedrine, F.; Monsuez, B.; Yen, K.; Matsuura, T.; Edwards, R.T.; Tveretina, O.; Fino, M.H.; O'Riordan, A.P.; Labiak, G.; Gaur, M.S.; Chang, J.; Chung, Y.-C.; Derezinska, A.; Cho, K.-R.; Zhang, Y.; Liutkevičius, R.; Zeng, Y.; Vasudevan, D.P.; Bukowiec, A.; Kitsos, P.; Goudarzi, M.; Dong, J.S. ; Bhalla, A.; Al-Khalili, D.; Navabi, Z.; Zinchenko, L.; Anjum, M.A.; Narasimha, D.L.; Hughes, D.; Tadjouddine, E.M.; Wang, J.; Kumar, A.P.S.; Jaisankar, N.; Mansoor, A.; Hollands, S.; Mohammadi, S.; Klein, F.; Westermann, P.; English, T.; Planas, M.M.; Chung, C.; Chakrabarti, A.; Lei, C.-U.; Bamakhrama, M.; Naik, B.R.; Harte, S.; Yin, A.; Giancardi, L.; El-Din Mady, A.; Joseph, A.; Khandekar, P.D.; Pandey, H.M.; Bharti, V.; O'Mullane, M.; Chen, C.
Showing results 65 to 84 of 127 < previous   next >