Browsing by Author HA YAJUN

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Showing results 47 to 59 of 59 < previous 
Issue DateTitleAuthor(s)
2013Quality-driven dynamic scheduling for real-time adaptive applications on multiprocessor systemsYu, H.; Ha, Y. ; Veeravalli, B. 
2006Resource manager for non-preemptive heterogeneous multiprocessor system-on-chipKumar, A.; Mesman, B.; Theelen, B.; Corporaal, H.; Yajun, H. 
2013Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodologyZhao, W.; Ha, Y. ; Hoo, C.H.; Alvarez, A.B.
2013SAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interfaceChen, Y.; Wang, Y.; Ha, Y. ; Felipe, M.R.; Ren, S.; Aung, K.M.M.
2008SFPGA - A scalable switch based FPGA architecture and design methodologyFernando, S. ; Chen, X.; Ha, Y. 
2009sFPGA2 - A scalable gals FPGA architecture and design methodologySyed, R.; Chen, X.; Ha, Y. ; Veeravalli, B. 
2008Statistical noise margin estimation for sub-threshold combinational circuitsPu, Y.; De Gyvez, J.P.; Corporaal, H.; Ha, Y. 
2013The architecture and placement algorithm for a uni-directional routing based 3D FPGAHou, J.; Yu, H.; Ha, Y. ; Liu, X.
2014Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCsYu, H.; Syed, R.; Ha, Y. 
2008Tighter WCET analysis of input dependent programs with classified-cache memory architectureYanhui, L.; Fernando, S.D. ; Heng, Y.; Xiaolei, C.; Yajun, H. ; Teng, T.T. 
2013TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCsHaque, M.S.; Kumar, A. ; Ha, Y. ; Wu, Q.; Luo, S.
2010Ultra storage-efficient time digitizer for pseudorandom single photon counter implemented on a field-programmable gate arrayTian, H.; Fernando, S. ; Soon, H.W.; Qiang, Z.; Zhang, C.; Ha, Y. ; Chen, N. 
2007V t balancing and device sizing towards high yield of sub-threshold static logic gatesPu, Y.; De Gyvez, J.P.; Corporaal, H.; Ha, Y.