Skip navigation
IVLE
Email
Library
Map
Calendar
Home
Research Outputs
View research outputs
Deposit publication / dataset
Researchers
Help
FAQs
Contact us
Guidelines
Log in
ScholarBank@NUS
Research Outputs
Browsing by Author
HA YAJUN
Enter a last name
Select a letter below to browse by last name or type
0-9
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
Or
Results/Page
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Showing results 43 to 59 of 59
< previous
Refman
EndNote
Bibtex
RefWorks
Excel
CSV
PDF
Send via email
Issue Date
Title
Author(s)
2012
Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs
Wang, C.
;
Li, X.
;
Zhou, X.
;
Ha, Y.
2010
Performance-cost analyses software for H.264 forward/inverse integer transform
Do, T.T.T.
;
Le, T.M.
;
Nguyen, B.P.
;
Ha, Y.
2008
Providing both guaranteed and best effort services using Spatial Division Multiplexing NoC with dynamic channel allocation and runtime reconfiguration
Lim, J.
;
Siow, E.H.
;
Ha, Y.
;
Meher, P.K.
18-Aug-2008
Pseudo-random single photon counting for time-resolved optical measurement
Zhang, Q.
;
Soon, H.W.
;
Tian, H.
;
Fernando, S.
;
Ha, Y.
;
Chen, N.G.
2013
Quality-driven dynamic scheduling for real-time adaptive applications on multiprocessor systems
Yu, H.
;
Ha, Y.
;
Veeravalli, B.
2006
Resource manager for non-preemptive heterogeneous multiprocessor system-on-chip
Kumar, A.
;
Mesman, B.
;
Theelen, B.
;
Corporaal, H.
;
Yajun, H.
2013
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology
Zhao, W.
;
Ha, Y.
;
Hoo, C.H.
;
Alvarez, A.B.
2013
SAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface
Chen, Y.
;
Wang, Y.
;
Ha, Y.
;
Felipe, M.R.
;
Ren, S.
;
Aung, K.M.M.
2008
SFPGA - A scalable switch based FPGA architecture and design methodology
Fernando, S.
;
Chen, X.
;
Ha, Y.
2009
sFPGA2 - A scalable gals FPGA architecture and design methodology
Syed, R.
;
Chen, X.
;
Ha, Y.
;
Veeravalli, B.
2008
Statistical noise margin estimation for sub-threshold combinational circuits
Pu, Y.
;
De Gyvez, J.P.
;
Corporaal, H.
;
Ha, Y.
2013
The architecture and placement algorithm for a uni-directional routing based 3D FPGA
Hou, J.
;
Yu, H.
;
Ha, Y.
;
Liu, X.
2014
Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs
Yu, H.
;
Syed, R.
;
Ha, Y.
2008
Tighter WCET analysis of input dependent programs with classified-cache memory architecture
Yanhui, L.
;
Fernando, S.D.
;
Heng, Y.
;
Xiaolei, C.
;
Yajun, H.
;
Teng, T.T.
2013
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
Haque, M.S.
;
Kumar, A.
;
Ha, Y.
;
Wu, Q.
;
Luo, S.
2010
Ultra storage-efficient time digitizer for pseudorandom single photon counter implemented on a field-programmable gate array
Tian, H.
;
Fernando, S.
;
Soon, H.W.
;
Qiang, Z.
;
Zhang, C.
;
Ha, Y.
;
Chen, N.
2007
V t balancing and device sizing towards high yield of sub-threshold static logic gates
Pu, Y.
;
De Gyvez, J.P.
;
Corporaal, H.
;
Ha, Y.