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Showing results 1 to 20 of 59
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Issue Date
Title
Author(s)
2015
A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor
Zhao W
;
Pan R
;
Ha Yajun
;
Yang Z
2007
A branch target instruction prefetchnig technique for improved performance
Gade, P.R.
;
Paily, R.
;
Ha, Y.
2013
A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm
Hoo, C.H.
;
Ha, Y.
;
Kumar, A.
2007
A fast reconfigurable and area efficient encryption engine using partial reconfiguration
Ye, Z.
;
Fernando, S.D.
;
Ha, Y.
;
Chen, N.
2011
A hilbert curve-based delay fault characterization method for FPGAs
Zhang, W.
;
Ha, Y.
2008
A low overhead fault tolerant FPGA with new connection box
Wong, F.
;
Ha, Y.
Apr-2001
A new CMOS buffer amplifier design used in low voltage MEMS interface circuits
Ha, Y.
;
Li, M.F.
;
Liu, A.Q.
2012
A power and cluster-aware technology mapping and clustering scheme for dual-VT FPGAs
Loke, W.T.
;
Ha, Y.
;
Zhao, W.
2007
A probabilistic approach to model resource contention for performance estimation of multi-featured media devices
Kumar, A.
;
Mesman, B.
;
Corporaal, H.
;
Theelen, B.
;
Ha, Y.
2008
An architecture and timing-driven routing algorithm for area-efficient fPGAs with time-multiplexed interconnects
Liu, H.
;
Chen, X.
;
Ha, Y.
2010
An area-efficient dynamically reconfigurable spatial division multiplexing Network-on-Chip with static throughput guarantee
Yang, Z.J.
;
Kumar, A.
;
Ha, Y.
2013
An area-efficient shuffling scheme for AES implementation on FPGA
Wang, Y.
;
Ha, Y.
2008
An area-efficient timing-driven routing algorithm for scalable FPGAs with time-multiplexed interconnects
Liu, H.
;
Chen, X.
;
Ha, Y.
2006
An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
Pu, Y.
;
Ha, Y.
Apr-2005
An embedded system to support tele-medical activity
Hui, N.J.
;
Lih, T.C.
;
Jun, H.Y.
2009
An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials
Meher, P.K.
;
Ha, Y.
;
Lee, C.-Y.
Mar-2010
An ultra-low-energy multi-standard JPEG Co-processor in 65 nm CMOS with sub/near threshold upply voltage
Pu, Y.
;
De Gyvez, J.P.
;
Corporaal, H.
;
Ha, Y.
2009
An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply
Pu, Y.
;
De Gyvez, J.P.
;
Corporaal, H.
;
Ha, Y.
Mar-2008
Analyzing composability of applications on MPSoC platforms
Kumar, A.
;
Mesman, B.
;
Theelen, B.
;
Corporaal, H.
;
Ha, Y.
2010
B*-tree based variability-aware floorplanning
Zhang, W.
;
Srivastava, S.
;
Ha, Y.