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HA YAJUN
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Showing results 50 to 59 of 59
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Issue Date
Title
Author(s)
2013
SAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface
Chen, Y.
;
Wang, Y.
;
Ha, Y.
;
Felipe, M.R.
;
Ren, S.
;
Aung, K.M.M.
2008
SFPGA - A scalable switch based FPGA architecture and design methodology
Fernando, S.
;
Chen, X.
;
Ha, Y.
2009
sFPGA2 - A scalable gals FPGA architecture and design methodology
Syed, R.
;
Chen, X.
;
Ha, Y.
;
Veeravalli, B.
2008
Statistical noise margin estimation for sub-threshold combinational circuits
Pu, Y.
;
De Gyvez, J.P.
;
Corporaal, H.
;
Ha, Y.
2013
The architecture and placement algorithm for a uni-directional routing based 3D FPGA
Hou, J.
;
Yu, H.
;
Ha, Y.
;
Liu, X.
2014
Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs
Yu, H.
;
Syed, R.
;
Ha, Y.
2008
Tighter WCET analysis of input dependent programs with classified-cache memory architecture
Yanhui, L.
;
Fernando, S.D.
;
Heng, Y.
;
Xiaolei, C.
;
Yajun, H.
;
Teng, T.T.
2013
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
Haque, M.S.
;
Kumar, A.
;
Ha, Y.
;
Wu, Q.
;
Luo, S.
2010
Ultra storage-efficient time digitizer for pseudorandom single photon counter implemented on a field-programmable gate array
Tian, H.
;
Fernando, S.
;
Soon, H.W.
;
Qiang, Z.
;
Zhang, C.
;
Ha, Y.
;
Chen, N.
2007
V t balancing and device sizing towards high yield of sub-threshold static logic gates
Pu, Y.
;
De Gyvez, J.P.
;
Corporaal, H.
;
Ha, Y.