Browsing by Author HA YAJUN

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Issue DateTitleAuthor(s)
2008An area-efficient timing-driven routing algorithm for scalable FPGAs with time-multiplexed interconnectsLiu, H.; Chen, X.; Ha, Y. 
2006An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic modelPu, Y.; Ha, Y. 
Apr-2005An embedded system to support tele-medical activityHui, N.J.; Lih, T.C.; Jun, H.Y. 
2009An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomialsMeher, P.K.; Ha, Y. ; Lee, C.-Y.
Mar-2010An ultra-low-energy multi-standard JPEG Co-processor in 65 nm CMOS with sub/near threshold upply voltagePu, Y.; De Gyvez, J.P.; Corporaal, H.; Ha, Y. 
2009An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supplyPu, Y.; De Gyvez, J.P.; Corporaal, H.; Ha, Y. 
Mar-2008Analyzing composability of applications on MPSoC platformsKumar, A. ; Mesman, B.; Theelen, B.; Corporaal, H.; Ha, Y. 
2010B*-tree based variability-aware floorplanningZhang, W.; Srivastava, S.; Ha, Y. 
2010Communication-aware application mapping and scheduling for NoC-based MPSoCsYu, H.; Ha, Y. ; Veeravalli, B. 
2013Criticality-based routing for FPGAS with reverse body bias switch box architecturesLoke, W.T.; Zhao, W.; Ha, Y. 
2008Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGATian, H.; Fernando, S. ; Soon, H.W.; Ha, Y. ; Chen, N. 
2005Design of networked reconfigurable encryption engineFernando, S. ; Yajun, H. 
Apr-2005Design of seamless Protocol Switching Layer for Voice over Internet Protocol (VoIP) that switches between Bluetooth and IEEE 802.11Han, T.Y.; Thampi, A.K.; Sebastian, D.J.; Yajun, H.A. 
2005Design space exploration for arbitrary FPGA architecturesLee, C.S.; Ha, Y. 
2008Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systemsYu, H.; Veeravalli, B. ; Ha, Y. 
2013Dynamic scheduling of imprecise-computation tasks on real-time embedded multiprocessorsYu, H.; Veeravalli, B.; Ha, Y. ; Luo, S.
2011Error flatten logarithm approximation for graphics processing unitZhu, M.; Xiao, J.; Wanggen, W.; Yajun, H.A. 
2007Fast and accurate interval-based timing estimator for variability-aware FPGA physical synthesis toolsLee, C.S.; Loke, W.T.; Zhang, W.; Ha, Y. 
2013FPGA based Rekeying for cryptographic key management in Storage Area NetworkWang, Y.; Ha, Y. 
2013FPGA-based 40.9-gbits/s masked AES with area optimization for storage area networkWang, Y.; Ha, Y.