Skip navigation
IVLE
Email
Library
Map
Calendar
Home
Research Outputs
View research outputs
Deposit publication / dataset
Researchers
Help
FAQs
Contact us
Guidelines
Log in
ScholarBank@NUS
Research Outputs
Browsing by Author
SAMUDRA,GANESH S
Enter a last name
Select a letter below to browse by last name or type
0-9
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
Or
Results/Page
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Showing results 1 to 20 of 274
next >
Refman
EndNote
Bibtex
RefWorks
Excel
CSV
PDF
Send via email
Issue Date
Title
Author(s)
Oct-2000
120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit
Xu, S.
;
Gan, K.P.
;
Samudra, G.S.
;
Liang, Y.C.
;
Sin, J.K.O.
2008
5 nm gate length nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation technique
Liow, T.-Y.
;
Tan, K.-M.
;
Lee, R.T.P.
;
Zhu, M.
;
Tan, B.L.-H.
;
Samudra, G.S.
;
Balasubramanian, N.
;
Yeo, Y.-C.
2006
50 nm silicon-on-insulator N-MOSFET featuring multiple stressors: Silicon-carbon source/drain regions and tensile stress silicon nitride liner
Ang, K.-W.
;
Chui, K.-J.
;
Chin, H.-C.
;
Foo, Y.-L.
;
Du, A.
;
Deng, W.
;
Li, M.-F.
;
Samudra, G.
;
Balasubramanian, N.
;
Yeo, Y.-C.
2006
A CMOS compatible smart power synchronous rectifier
Lim, C.Y.
;
Liang, Y.C.
;
Samudra, G.S.
;
Balasubramanian, N.
2008
A complementary-I-MOS technology featuring SiGe channel and I-region for enhancement of impact-ionization, breakdown voltage, and performance
Toh, E.-H.
;
Wang, G.H.
;
Chan, L.
;
Lo, G.-Q.
;
Sylvester, D.
;
Heng, C.-H.
;
Samudra, G.
;
Yeo, Y.-C.
2010
A computational study on the device performance of graphene nanoribbon heterojunction tunneling FETs based on bandgap engineering
Lam, K.-T.
;
Da, H.
;
Chin, S.-K.
;
Samudra, G.
;
Yeo, Y.-C.
;
Liang, G.
Feb-2008
A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance
Toh, E.-H.
;
Wang, G.H.
;
Chan, L.
;
Samudra, G.
;
Yeo, Y.-C.
May-2003
A dual BARC method for lithography and etch for Dual damascene with low K
Mukherjee-Roy, M.
;
Bliznetsov, V.
;
Samudra, G.
Sep-2004
A FinFET and Tri-gate MOSFET's channel structure patterning and its influence on the device performance
Jagar, S.
;
Singh, N.
;
Mehta, S.S.
;
Agrawal, N.
;
Samudra, G.
;
Balasubramanian, N.
Feb-2008
A high-stress liner comprising diamond-like carbon (DLC) for strained p-channel MOSFET
Tan, K.-M.
;
Zhu, M.
;
Fang, W.-W.
;
Yang, M.
;
Liow, T.-Y.
;
Lee, R.T.P.
;
Hoe, K.M.
;
Tung, C.-H.
;
Balasubramanian, N.
;
Samudra, G.S.
;
Yeo, Y.-C.
Oct-2003
A new approach for eliminating unwanted patterns in attenuated phase shift masks
Mukherjee-Roy, M.
;
Singh, N.
;
Mehta, S.S.
;
Samudra, G.S.
2007
A new liner stressor with very high intrinsic stress (> 6 GPa) and low permittivity comprising diamond-like carbon (DLC) for strained p-channel transistors
Tan, K.-M.
;
Zhu, M.
;
Fang, W.-W.
;
Yang, M.
;
Liow, T.-Y.
;
Lee, R.T.P.
;
Hoe, K.M.
;
Tung, C.-H.
;
Balasubramanian, N.
;
Samudra, G.S.
;
Yeo, Y.-C.
Aug-1997
A new modeling technique for mixed-mode simulation of CMOS circuits
Samudra, G.
;
Lee, T.K.
2009
A new robust non-local algorithm for band-to-band tunneling simulation and its application to tunnel-FET
Shen, C.
;
Yang, L.T.
;
Toh, E.-H.
;
Heng, C.-H.
;
Samudra, G.S.
;
Yeo, Y.-C.
Mar-2011
A new robust non-local algorithm for band-to-band tunneling simulation and its application to tunnel-FET
Shen, C.
;
Yang, L.-T.
;
Samudra, G.
;
Yeo, Y.-C.
2008
A new salicidation process with solid Antimony (Sb) segregation (SSbS) for achieving sub-0.1 eV effective schottky barrier height and parasitic series resistance reduction in N-channel transistors
Wong, H.-S.
;
Koh, A.T.-Y.
;
Chin, H.-C.
;
Lee, R.T.-P.
;
Chan, L.
;
Samudra, G.
;
Yeo, Y.-C.
2008
A new source/drain germanium-enrichment process comprising Ge deposition and laser-induced local melting and recrystallization for P-FET performance enhancement
Liu, F.
;
Wong, H.-S.
;
Ang, K.-W.
;
Zhu, M.
;
Wang, X.
;
Lai, D.M.-Y.
;
Lim, P.-C.
;
Tan, B.L.H.
;
Tripathy, S.
;
Oh, S.-A.
;
Samudra, G.S.
;
Balasubramanian, N.
;
Yeo, Y.-C.
2004
A new surface rounding technique for deep submicron CMOS transistor
Tat, C.Y.
;
Goh, W.L.
;
Shenp, A.D.
;
Meng, T.K.
;
Samudra, G.S.
;
Hung, C.L.
2005
A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistor
Toh, E.-H.
;
Wang, G.H.
;
Lo, G.-Q.
;
Balasubramanian, N.
;
Tung, C.-H.
;
Benistant, F.
;
Chan, L.
;
Samudra, G.
;
Yeo, Y.-C.
11-Jun-2008
A pseudopotential method for investigating the surface roughness effect in ultrathin body transistors
Zhu, Z.-G.
;
Liang, G.
;
Li, M.-F.
;
Samudra, G.