Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/99283
Title: Failure of instruction prefetching of 8088/286/ 386 microprocessors in XT/AT systems
Authors: Lua, K.T. 
Keywords: 80286
80386
8088
Instruction timing
Pipeline
Prefetch
Issue Date: Sep-1990
Citation: Lua, K.T. (1990-09). Failure of instruction prefetching of 8088/286/ 386 microprocessors in XT/AT systems. Microprocessing and Microprogramming 29 (2) : 97-106. ScholarBank@NUS Repository.
Abstract: The Intel 8088/286/386 microprocessors are designed with instruction prefetch and pipeline features to increase their bus utilization and system throughput. However, there are many occasions where these features fail and instruction executions are lengthened. The failure of 8088/286/386 instruction prefetch and pipeline working under PC/XT and PC/AT environment are studied in this paper. We investigate the effect of (i) memory refresh, (ii) the heavy bus utilization and (iii) memory access wiat state on the performance of the 8088/286/386 prefetchers. © 1990.
Source Title: Microprocessing and Microprogramming
URI: http://scholarbank.nus.edu.sg/handle/10635/99283
ISSN: 01656074
Appears in Collections:Staff Publications

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