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|Title:||High density metal oxide (ZnO) nanopatterned platforms for electronic applications|
|Source:||Suresh, V.,Huang, M.S.,Srinivasan, M.P.,Krishnamoorthy, S. (2013). High density metal oxide (ZnO) nanopatterned platforms for electronic applications. Materials Research Society Symposium Proceedings 1498 : 255-261. ScholarBank@NUS Repository. https://doi.org/10.1557/opl.2013.344|
|Abstract:||Fabrication methodologies with high precision and tenability for nanostructures of metal and metal oxides are widely explored for engineering devices such as solar cells, sensors, non-volatile memories (NVM) etc. In this direction, metal and metal oxide nanopatterned arrays are the state-of-the-art platforms upon which the device structures are built where the tunable orderly arrangement of the nanostructures enhances the device performance. We describe here a coalition of fabrication protocols that employ block copolymer self-assembly and nanoimprint lithography (NIL) to obtain metal oxide nanopatterns with sub-100 nm spatial resolution. The protocols are easily scalable down to sub-50 nm and below. Nanopatterned arrays of ZnO created by using NIL assisted templates through area selective atomic layer deposition (ALD) and radio frequency (RF) sputtering find application in NVM and photovoltaics. We have employed NIL that produced nanoporous polymer templates using Si molds derived from block copolymer lithography (BCL) for pattern transfer into ZnO. The resulting ZnO nanoarrays were highly dense (8.6 × 109 nanofeatures per cm2) exhibiting periodic feature to feature spacing and width that replicated the geometric attributes of the template. Such nanopatterns find application in NVM, where a change in the density and periodicity of the arrays influences the charge storage characteristics. The above assembly and patterning protocols were employed to fabricate metal-oxide-semiconductor (MOS) capacitor devices for investigating application in NVM. Patterned ZnO nanoarrays were used as charge storage centres for the MOS capacitor devices. Preliminary results upon investigating the flash memory performance showed good flat-band voltage hysteresis window at a relatively low operating voltage due to high charge trap density. © 2013 Materials Research Society.|
|Source Title:||Materials Research Society Symposium Proceedings|
|Appears in Collections:||Staff Publications|
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