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|Title:||Bed of nails: Fine pitch wafer-level packaging interconnects for high performance nano devices|
|Source:||Rao, V.S.,Kripesh, V.,Yoon, S.W.,Witarsa, D.,Tay, A.A.O. (2005). Bed of nails: Fine pitch wafer-level packaging interconnects for high performance nano devices. Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005 2 : 658-663. ScholarBank@NUS Repository.|
|Abstract:||The rapid advances in IC design and fabrication continue to challenge electronics packaging technology in terms of fine pitch, high performance, low cost and better reliability. The shift towards the nano ICs with feature size less than 90nm, increases the demand for higher I/O count per integrated circuit (IC) chip. The demands for high pin count and the increasing packaging density requirements in high performance device packaging is necessitating less than 100 microns pitch chip to substrate interconnection technologies. However, the long-term board level reliability of packages with large distance from neutral point (DNP) is not yet fully solved. Wafer level packaging is the promising solution to meet the cost and fine pitch requirements. Currently, the CTE mismatch between Si chip and substrate serves as the biggest bottleneck in the conventional chip-to-substrate interconnection technology and this becomes even more critical with reduction in pitch of the interconnects. Added to this, even the assembly yield of such fine pitch interconnections also serves as one of the other biggest challenges. In this paper, the Bed of Nails (BoN) interconnection technology on a 20 × 20 mm2 test chip with 2256 and 36,481 I/Os in 3 depopulated rows and fully populated, respectively, are presented. This technology has been developed to achieve a fine pitch of 100 microns and high density interconnections. The test demonstrators are designed with same number of I/Os and fabricated. Compliance is also provided by giving high stand-off height of interconnect ( > 2 aspect ratio) compared to the conventional solder bumping where the aspect ratio equals one. The board level reliability test is performed on the 20 × 20 mm2 test chip with depopulated BoN interconnects, with and without underfill, under temperature cycling at the range of-40°C to 125°C. ©2005 IEEE.|
|Source Title:||Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005|
|Appears in Collections:||Staff Publications|
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