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|Title:||Sub 50nm strained n-FETs formed on silicon-germanium-on-insulator substrates and the integration of silicon source/drain stressors|
|Source:||Wang, G.H.,Toh, E.-H.,Hoe, K.-M.,Tripathy, S.,Lo, G.-Q.,Samudra, G.,Yeo, Y.-C. (2007). Sub 50nm strained n-FETs formed on silicon-germanium-on-insulator substrates and the integration of silicon source/drain stressors. Materials Research Society Symposium Proceedings 995 : 49-54. ScholarBank@NUS Repository.|
|Abstract:||Silicon (Si) source and drain (S/D) regions have been successfully integrated in thin-body silicon-germanium-on-insulator (SGOI) n-FETs. The selectively grown Si S/D induces uniaxial tensile strain in the SiGe channel. Lattice mismatch between the silicon S/D region and the SiGe channel was exploited to induce lateral tensile strain and vertical compressive strain in the channel, leading to enhancement in electron mobility. Devices with gate length LG down to 50 nm were fabricated. For transistors fabricated on Si0.60Ge0.40-on-insulator substrates, devices with Si S/D give 40% higher saturation drain current IDsatthan devices with Si0.60Ge0.40 S/D. When the Ge content is reduced in Si0.75Ge0.25-on-insulator substrates, the lattice mismatch between the S/D and the channel for devices with Si S/D is reduced, and a lower IDsat enhancement of 27% is reported over devices with Si 0.75Ge0.25 S/D and channel regions. Analyses of contributions from the tensile strain to mobility enhancement and performance improvement are discussed. © 2007 Materials Research Society.|
|Source Title:||Materials Research Society Symposium Proceedings|
|Appears in Collections:||Staff Publications|
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