Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISDRS.2007.4422229
Title: Strained Si n-FET featuring compliant SiGe Stress Transfer Layer (STL) and Si0.98C0.02 source/drain stressors for performance enhancement
Authors: Wang, G.H.
Toh, E.-H.
Weeks, D.
Landin, T.
Spear, J.
Tung, C.H.
Thomas, S.G.
Samudra, G. 
Yeo, Y.-C. 
Issue Date: 2007
Citation: Wang, G.H.,Toh, E.-H.,Weeks, D.,Landin, T.,Spear, J.,Tung, C.H.,Thomas, S.G.,Samudra, G.,Yeo, Y.-C. (2007). Strained Si n-FET featuring compliant SiGe Stress Transfer Layer (STL) and Si0.98C0.02 source/drain stressors for performance enhancement. 2007 International Semiconductor Device Research Symposium, ISDRS : -. ScholarBank@NUS Repository. https://doi.org/10.1109/ISDRS.2007.4422229
Abstract: We report the first demonstration of an n-channel transistor (n-FET) featuring a compliant Si0.75Ge0.25 Stress Transfer Layer (STL) and in situ doped Si0.98C0.02 source/drain (S/D) stressors for performance enhancement. Due to the stress coupling between Si0.98C0.02 and the compliant SiGe STL, additional strain is imparted to the Si channel. Devices with gate length LG down to 30 nm were fabricated. The enhanced strain effects resulted in 65% drive current improvement in strained n-FETs over control n-FETs for a given DIBL of 0.20V/V. ©2007 IEEE.
Source Title: 2007 International Semiconductor Device Research Symposium, ISDRS
URI: http://scholarbank.nus.edu.sg/handle/10635/84234
ISBN: 1424418917
DOI: 10.1109/ISDRS.2007.4422229
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