Please use this identifier to cite or link to this item: https://doi.org/10.1109/IEDM.2007.4418882
Title: Silicon-germanium-tin (SiGeSn) source and drain stressors formed by Sn implant and laser annealing for strained silicon-germanium channel P-MOSFETs
Authors: Wang, G.H.
Toh, E.-H.
Wang, X.
Seng, D.H.L.
Tripathy, S.
Osipowicz, T.
Chan, T.K.
Hoe, K.M.
Balakumar, S.
Tung, C.H.
Lo, G.-Q.
Samudra, G. 
Yeo, Y.-C. 
Issue Date: 2007
Source: Wang, G.H., Toh, E.-H., Wang, X., Seng, D.H.L., Tripathy, S., Osipowicz, T., Chan, T.K., Hoe, K.M., Balakumar, S., Tung, C.H., Lo, G.-Q., Samudra, G., Yeo, Y.-C. (2007). Silicon-germanium-tin (SiGeSn) source and drain stressors formed by Sn implant and laser annealing for strained silicon-germanium channel P-MOSFETs. Technical Digest - International Electron Devices Meeting, IEDM : 131-134. ScholarBank@NUS Repository. https://doi.org/10.1109/IEDM.2007.4418882
Abstract: We report a new silicon-germanium-tin (SiGeSn) source and drain stressor with large lattice-mismatch with respect to Si or SiGe for channel strain engineering, and its integration in a SiGe-channel p-FET for performance enhancement. A novel CMOS-compatible process was developed to incorporate Sn in SiGe S/D with high levels of Sn-substitutionality: Sn implant into Si 0.75Ge0.25 source and drain (S/D) regions, followed by either excimer Laser annealing (LA) or Solid Phase Epitaxy (SPE) to restore S/D crystallinity. Sub-50 nm p-FETs were fabricated. With a substitutional Sn concentration of 8% in SiGe S/D regions, equivalent to forming Si 0.4Ge0.6 in the S/D region, enhancement of I Dsat and hole mobility are 82% and 135%, respectively, over control p-FETs without Sn incorporation. With the first demonstration of SiGeSn S/D stressors, we provide a technology extension to SiGe S/D technology for further p-FET enhancement. © 2007 IEEE.
Source Title: Technical Digest - International Electron Devices Meeting, IEDM
URI: http://scholarbank.nus.edu.sg/handle/10635/84182
ISSN: 01631918
DOI: 10.1109/IEDM.2007.4418882
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