Please use this identifier to cite or link to this item: https://doi.org/10.1109/ESSDER.2005.1546663
Title: Scalability and reliability of TaN/HfN/HfO2 gate stacks fabricated by a high temperature process
Authors: Kang, J.F.
Yu, H.Y.
Ren, C.
Yang, H.
Sa, N.
Liu, X.Y.
Han, R.Q.
Li, M.-F. 
Chan, D.S.H. 
Kwong, D.-L.
Issue Date: 2005
Source: Kang, J.F., Yu, H.Y., Ren, C., Yang, H., Sa, N., Liu, X.Y., Han, R.Q., Li, M.-F., Chan, D.S.H., Kwong, D.-L. (2005). Scalability and reliability of TaN/HfN/HfO2 gate stacks fabricated by a high temperature process. Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference 2005 : 375-378. ScholarBank@NUS Repository. https://doi.org/10.1109/ESSDER.2005.1546663
Abstract: The scalability and reliability issues of the CVD-HfO2 gate dielectrics with PVD TaN/HfN electrodes, fabricated by a high temperature process, were addressed. The equivalent oxide thickness (EOT) is aggressively scaled down to 0.75 nm and 0.95 nm for MOS capacitor and MOSFET, respectively. Low preexisting traps in the TaN/HfN/HfO2 gate stacks were observed, which could be attributed to the high temperature post gate annealing process. The excellent reliability characteristics were achieved in the TaN/HfN/HfO 2 gate stacks. © 2005 IEEE.
Source Title: Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference
URI: http://scholarbank.nus.edu.sg/handle/10635/84155
ISBN: 0780392035
DOI: 10.1109/ESSDER.2005.1546663
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