Please use this identifier to cite or link to this item: https://doi.org/10.1109/ICSICT.2006.306050
Title: Planar and multiple-gate transistors with silicon-carbon source/drain
Authors: Yeo, Y.-C. 
Issue Date: 2007
Source: Yeo, Y.-C. (2007). Planar and multiple-gate transistors with silicon-carbon source/drain. ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings : 39-42. ScholarBank@NUS Repository. https://doi.org/10.1109/ICSICT.2006.306050
Abstract: We explore technology options for the enhancement of electron mobility in n-FETs, focusing on channel strain engineering using lattice-mismatched source/drain (S/D) materials. By employing silicon-carbon (Si 1-yCy) in the S/D regions, lateral tensile strain in the Si channel is induced for electron mobility and drive current IDsat improvement. Further performance enhancement is achieved by the combination of multiple-stressors, e.g. Si1-yCy S/D and silicon nitride SiN liner stressor. This is demonstrated on bulk planar transistors, silicon-on-insulator planar transistors, and multiple-gate transistors. Process integration issues and strain enhancement approaches are discussed. © 2006 IEEE.
Source Title: ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
URI: http://scholarbank.nus.edu.sg/handle/10635/84099
ISBN: 1424401615
DOI: 10.1109/ICSICT.2006.306050
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
There are no files associated with this item.

SCOPUSTM   
Citations

2
checked on Feb 20, 2018

Page view(s)

5
checked on Feb 23, 2018

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.