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|Title:||New insights of BTI degradation in MOSFETs with SiON gate dielectrics|
|Authors:||Li, M.-F. |
|Source:||Li, M.-F., Huang, D., Liu, W.J., Liu, Z.Y., Huang, X.Y. (2009). New insights of BTI degradation in MOSFETs with SiON gate dielectrics. ECS Transactions 19 (2) : 301-318. ScholarBank@NUS Repository. https://doi.org/10.1149/1.3122098|
|Abstract:||It is widely recognized that recovery during measurement delay seriously misleads the BTI phenomena. We have developed a modified Charge Pumping (MCP) method to measure the interface trap generation under stress with negligible recovery during measurement delay. The method simply extends the inversion level Vinv of the CP pulse to the stress voltage and keeps the duty cycle of Kinv as large as possible, therefore the stress is almost "on" during measurement. For the first time, we developed a diagram representation of CP process and used to the physical analysis for the contribution and exclusion of slow oxide charge contribution in the CP current of this MCP method. Using this MCP method and the fast pulsed I d-Vg method (FPM) we developed in the past, we systematically investigate and compare the NBTI degradation of p-MOSFETs with thermal (TNO) and plasma (PNO) nitrided SiON gate dielectrics with the same nitrogen surface concentration. We also systematically measure the interface trap degradations in four configurations of NBTI and PBTI stresses for both n-MOSFETs and p-MOSFETs. The following results are achieved: (1) The oxide charge induced degradation in TNO SiON devices is several times larger than those in PNO devices under the same stress condition, due to the larger charge moment in the gate dielectrics of the TNO devices. (2) Although TNO and PNO devices have very different oxide trap NBTI degradation behaviors, however both types of devices have the similar interface trap degradation behavior. The temperature dependent power law index n of the interface trap generation is linear dependent of temperature when T is lower than 100°C and is saturated at around 0.18 when T is higher than 100°C. The interface trap activation energy EA is 0.77 eV. (3) There are interface trap generations under stresses for all four different configurations. The generation rates under comparable stress conditions are the highest for p-MOSFETs under positive stress and lowest for n-MOSFETs under positive stress. The experimental data imply that hot holes are more effective in interface trap generation. © The Electrochemical Society.|
|Source Title:||ECS Transactions|
|Appears in Collections:||Staff Publications|
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