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|Title:||Methodology for optimizing gain and noise figure performance of CMOS LNAs at 60GHz and beyond|
|Keywords:||CMOS digital integrated circuits|
|Source:||Yeo, S.-B., Brinkhoff, J., Lin, F., Xu, Y.P. (2009). Methodology for optimizing gain and noise figure performance of CMOS LNAs at 60GHz and beyond. 2009 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2009 : 241-244. ScholarBank@NUS Repository. https://doi.org/10.1109/RFIT.2009.5383709|
|Abstract:||This paper describes a technique of finding the noise figure of a 60GHz LNA by extracting the equivalent noise resistance (Rn) of a MOSFET through on-wafer noise figure (F50) measurements at lower frequency (up to 18GHz), while the other three noise parameters are extracted from S-parameter measurements beyond 60GHz. This paper demonstrates how the gain-noise figure performance is optimized using extrapolated noise parameters and RF small signal models, with the measurement data (using 67GHz noise source) closely matching the simulated noise figure (extracted using 18GHz noise source) and gain performance at 60GHz. © 2009 IEEE.|
|Source Title:||2009 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2009|
|Appears in Collections:||Staff Publications|
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