Please use this identifier to cite or link to this item: https://doi.org/10.1109/SISPAD.2006.282857
Title: Interface barrier abruptness and work function requirements for scaling Schottky source-drain MOS transistors
Authors: Agrawal, N.
Chen, J. 
Hui, Z.
Yeo, Y.-C. 
Lee, S. 
Chan, D.S.H. 
Li, M.-F. 
Samudra, G.S. 
Keywords: Dual slope
Metal gate
Metal source/drain
Schottky source-drain
TBGD
Issue Date: 2007
Citation: Agrawal, N.,Chen, J.,Hui, Z.,Yeo, Y.-C.,Lee, S.,Chan, D.S.H.,Li, M.-F.,Samudra, G.S. (2007). Interface barrier abruptness and work function requirements for scaling Schottky source-drain MOS transistors. International Conference on Simulation of Semiconductor Processes and Devices, SISPAD : 139-142. ScholarBank@NUS Repository. https://doi.org/10.1109/SISPAD.2006.282857
Abstract: Schottky source-drain (S/D) MOS transistor coupled with metal gate is a promising alternative to the conventional poly-Si gate and doped S/D MOSFET technology [1-2]. This paper explores through simulations the effect of metal S/D WF and the gradual change of barrier profile at the metal-semiconductor interface and in the few nanometers space around it on the n/p channel device performance. We present the S/D workfunction (WF) requirements for ultra short channel device design for the first time. Through modeling and fabrication, we also present the underlying physical explanation behind the existence of dual slope in Id-Vg characteristics of metal S/D and Gate MOSFETs. © 2006 IEEE.
Source Title: International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
URI: http://scholarbank.nus.edu.sg/handle/10635/83854
ISBN: 1424404045
DOI: 10.1109/SISPAD.2006.282857
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