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Please use this identifier to cite or link to this item: https://doi.org/10.1149/1.3572300
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dc.titleHigh-k integration and interface engineering for III-V MOSFETs
dc.contributor.authorOh, H.J.
dc.contributor.authorSumarlina, A.B.S.
dc.contributor.authorLee, S.J.
dc.date.accessioned2014-10-07T04:45:18Z
dc.date.available2014-10-07T04:45:18Z
dc.date.issued2011
dc.identifier.citationOh, H.J., Sumarlina, A.B.S., Lee, S.J. (2011). High-k integration and interface engineering for III-V MOSFETs. ECS Transactions 35 (4) : 481-495. ScholarBank@NUS Repository. https://doi.org/10.1149/1.3572300
dc.identifier.isbn9781566778657
dc.identifier.issn19385862
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83798
dc.description.abstractIn this work, we report the comprehensive study of performance enhancement of InGaAs n-MOSFET by plasma PH3 passivation. The calibrated plasma PH3 passivation of the InGaAs surface before CVD high-k dielectric deposition significantly improves interface quality, resulting in suppressed frequency dispersion in C-V, increase in drive-current with high electron mobility, and excellent thermal stability. ©The Electrochemical Society.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1149/1.3572300
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1149/1.3572300
dc.description.sourcetitleECS Transactions
dc.description.volume35
dc.description.issue4
dc.description.page481-495
dc.identifier.isiut000302650100029
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