Enhanced performance in strained n-FET with double-recessed Si:C source/drain and lattice-mismatched SiGe strain-transfer structure (STS)

Abstract

We report on further performance optimization in a novel n-channel transistor (n-FET) with beneath-the-channel strain-transfer structure (STS) and embedded silicon-carbon source/drain (Si:C S/D) stressors. The incorporation of SiGe STS couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. In addition, a two-step recess-etch was used to bring the double-recessed S/D stressors in closer proximity, increasing their lattice interactions with the channel and the STS, thereby significantly increasing the saturation drive current I on enhancement over control devices. ©2007 IEEE.