Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISDRS.2007.4422277
Title: Enhanced performance in strained n-FET with double-recessed Si:C source/drain and lattice-mismatched SiGe strain-transfer structure (STS)
Authors: Ang, K.-W.
Wong, H.-S.
Balasubramanian, N.
Samudra, G. 
Yeo, Y.-C. 
Issue Date: 2007
Source: Ang, K.-W.,Wong, H.-S.,Balasubramanian, N.,Samudra, G.,Yeo, Y.-C. (2007). Enhanced performance in strained n-FET with double-recessed Si:C source/drain and lattice-mismatched SiGe strain-transfer structure (STS). 2007 International Semiconductor Device Research Symposium, ISDRS : -. ScholarBank@NUS Repository. https://doi.org/10.1109/ISDRS.2007.4422277
Abstract: We report on further performance optimization in a novel n-channel transistor (n-FET) with beneath-the-channel strain-transfer structure (STS) and embedded silicon-carbon source/drain (Si:C S/D) stressors. The incorporation of SiGe STS couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. In addition, a two-step recess-etch was used to bring the double-recessed S/D stressors in closer proximity, increasing their lattice interactions with the channel and the STS, thereby significantly increasing the saturation drive current I on enhancement over control devices. ©2007 IEEE.
Source Title: 2007 International Semiconductor Device Research Symposium, ISDRS
URI: http://scholarbank.nus.edu.sg/handle/10635/83701
ISBN: 1424418917
DOI: 10.1109/ISDRS.2007.4422277
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