Please use this identifier to cite or link to this item: https://doi.org/10.1116/1.1690258
Title: Direct trim etching process of Si/SiO2 gate stacks using 193 nm ArF patterns
Authors: Tan, K.M.
Yoo, W.J. 
Ma, H.H.H. 
Li, F.
Chan, L.
Issue Date: Jul-2004
Citation: Tan, K.M., Yoo, W.J., Ma, H.H.H., Li, F., Chan, L. (2004-07). Direct trim etching process of Si/SiO2 gate stacks using 193 nm ArF patterns. Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films 22 (4) : 1500-1505. ScholarBank@NUS Repository. https://doi.org/10.1116/1.1690258
Abstract: A polysilicon gate of 30 nm length was fabricated by direct trimming of a gate stack using a 193 nm photoresist process and by trimming the polysilicon gate with HBr/Cl2 plasma chemistry in an inductively coupled plasma (ICP) etcher. HBr was found to be an effective trimming etchant due to its higher trimming rate. The inclusion of Sf6 and O2 to the plasma and the longer trimming time were found to effect the reduction in the polysilicon footprint effectively. The results show that the trimming rate increases with an increase in ICP power from 200 to 800 W and decreases with decreasing pressure.
Source Title: Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
URI: http://scholarbank.nus.edu.sg/handle/10635/83634
ISSN: 07342101
DOI: 10.1116/1.1690258
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
There are no files associated with this item.

SCOPUSTM   
Citations

2
checked on Nov 8, 2018

WEB OF SCIENCETM
Citations

2
checked on Oct 31, 2018

Page view(s)

57
checked on Nov 9, 2018

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.