Direct trim etching process of Si/SiO2 gate stacks using 193 nm ArF patterns
Tan, K.M. Yoo, W.J. Ma, H.H.H. Li, F. Chan, L.
Tan, K.M.
Li, F.
Chan, L.
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Abstract
A polysilicon gate of 30 nm length was fabricated by direct trimming of a gate stack using a 193 nm photoresist process and by trimming the polysilicon gate with HBr/Cl2 plasma chemistry in an inductively coupled plasma (ICP) etcher. HBr was found to be an effective trimming etchant due to its higher trimming rate. The inclusion of Sf6 and O2 to the plasma and the longer trimming time were found to effect the reduction in the polysilicon footprint effectively. The results show that the trimming rate increases with an increase in ICP power from 200 to 800 W and decreases with decreasing pressure.
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Source Title
Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
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Date
2004-07
DOI
10.1116/1.1690258
Type
Conference Paper