Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/83536
Title: Characteristics of sub-1 nm CVD HfO2 gate dielectrics with HfN electrodes for advanced CMOS applications
Authors: Kang, J.F.
Yu, H.Y. 
Ren, C.
Wang, X.P.
Li, M.-F. 
Chan, D.S.H. 
Liu, X.Y.
Han, R.Q.
Wang, Y.Y.
Kwong, D.-L.
Issue Date: 2004
Source: Kang, J.F.,Yu, H.Y.,Ren, C.,Wang, X.P.,Li, M.-F.,Chan, D.S.H.,Liu, X.Y.,Han, R.Q.,Wang, Y.Y.,Kwong, D.-L. (2004). Characteristics of sub-1 nm CVD HfO2 gate dielectrics with HfN electrodes for advanced CMOS applications. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 1 : 393-398. ScholarBank@NUS Repository.
Abstract: High quality thermal robust CVD-HfO2 gate dielectrics witli HfN electrodes were fabricated. The scalability of the HfN/HfO2 gate stack and the integration issues with CMOS devices were systematically investigated. The equivalent oxide thickness (EOT) is aggressively scaled down to 0.65 nm with low gate leakage and excellent reliability characteristics. High performance HfN/HfO2 gated nMOSFET with 0.95 run EOT was fabricated by using a gate-first process compatible with standard CMOS process flow. Significantly improved effective electron mobility is achieved in the device. The improved mobility is related to a high temperature post annealing process after HfO2 deposition in the gate-first process such as the S/D activation annealing, which could effectively reduce the charge traps in HfO2 films. A dual metal gate integration process for HfO 2 CMOS devices is demonstrated using a HfN dummy metal layer. In the process, the dummy HfN metal gate electrode was selectively removed from high-temperature annealed HfN/HfO2 gate stack by diluted hydrofluoric without causing any degradation to the underlying HfO2 gate dielectrics. Then two other metals with appropriate work functions for dual-gate CMOS, such as Ta for n-MOS and Ni for p-MOS were then re-deposited on HfO2 as the new gate electrodes. The resulting n- and p-MOS devices show a work function difference of ∼0.8 eV. © 2004 IEEE.
Source Title: International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
URI: http://scholarbank.nus.edu.sg/handle/10635/83536
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