Please use this identifier to cite or link to this item:
|Title:||Beneath-the-channel Strain-Transfer-Structure (STS) and embedded source/drain stressors for strain and performance enhancement of nanoscale MOSFETs|
|Citation:||Ang, K.-W., Lin, J., Tung, C.-H., Balasubramanian, N., Samudra, G., Yeo, Y.-C. (2007). Beneath-the-channel Strain-Transfer-Structure (STS) and embedded source/drain stressors for strain and performance enhancement of nanoscale MOSFETs. Digest of Technical Papers - Symposium on VLSI Technology : 42-43. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSIT.2007.4339719|
|Abstract:||We report the first demonstration of a novel transistor structure featuring a beneath-the-channel strain-transfer-structure (STS) and embedded source/drain (S/D) stressors for strain and performance enhancement. As compared to a transistor with standard S/D stressors, additional strain is imparted to the channel region by the STS due to coupling of its lattice interactions with the adjacent S/D stressors and the overlying channel region. Both strained n-FET with SiGe STS and silicon-carbon (SiC) S/D, and strained p-FET with SiC STS and SiGe S/D, were realized. The Ion performance of strained n- and p-FETs with STS and S/D stressors were enhanced by 42% and 60%, respectively, over unstrained control transistors for given. DIBL of 0.15 V/V.|
|Source Title:||Digest of Technical Papers - Symposium on VLSI Technology|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Nov 11, 2018
checked on Nov 2, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.