Please use this identifier to cite or link to this item: https://doi.org/10.1109/ASPDAC.2009.4796482
Title: An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials
Authors: Meher, P.K.
Ha, Y. 
Lee, C.-Y.
Issue Date: 2009
Citation: Meher, P.K.,Ha, Y.,Lee, C.-Y. (2009). An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC : 210-215. ScholarBank@NUS Repository. https://doi.org/10.1109/ASPDAC.2009.4796482
Abstract: In this paper, we derive a recursive algorithm for finite field multiplication over GF(2m) based on irreducible all- one-polynomials (AOP), where the modular reduction of degree is achieved by cyclic-left-shift without any logic operations. A regular and localized bit-level dependence graph (DG) is derived from the proposed algorithm and mapped into an array architecture, where the modular reduction is achieved by a serial-in parallel- out shift-register. The multiplier is optimized further to perform the accumulation of partial products by the T flip flops of the output register without XOR gates. It is interesting to note that the optimized structure consists of an array of (m + 1) AND gates between an array of (m+1) D flip flops and an array of (m+1) Tflip flops. The proposed structure therefore involves significantly less area and less computation time compared with the corresponding existing structures. ©2009 IEEE.
Source Title: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
URI: http://scholarbank.nus.edu.sg/handle/10635/83483
ISBN: 9781424427482
DOI: 10.1109/ASPDAC.2009.4796482
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