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|Title:||A simple CMOS self-aligned double-gate poly-Si TFT technology|
|Citation:||Xiong, Z.,Liu, H.,Zhu, C.,Sin, J.K.O. (2005). A simple CMOS self-aligned double-gate poly-Si TFT technology. Proceedings - Electrochemical Society PV 2004-15 : 87-91. ScholarBank@NUS Repository.|
|Abstract:||In this paper, a new CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and demonstrated. The self-alignment between the top-gate and the bottom-gate is realized by a back-light exposure step. The structure has an ultra-thin channel region (300Å) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain field and the fully-depletion of the ultra-thin channel. Moreover, for n-channel devices, the SADG TFT has 4.2 times higher on-current at high gate biases (Vgs=20 V). For p-channel devices, the SADG TFT has 3.6 times higher on-current at high gate biases (Vgs=-20 V).|
|Source Title:||Proceedings - Electrochemical Society|
|Appears in Collections:||Staff Publications|
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