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|Title:||A multichannel integrated circuit for neural spike detection based on EC-PC threshold estimation|
|Citation:||Wu, T.,Yang, Z. (2013). A multichannel integrated circuit for neural spike detection based on EC-PC threshold estimation. Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS : 779-782. ScholarBank@NUS Repository. https://doi.org/10.1109/EMBC.2013.6609616|
|Abstract:||In extracellular neural recording experiments, spike detection is an important step for information decoding of neuronal activities. An ASIC implementation of detection algorithms can provide substantial data-rate reduction and facilitate wireless operations. In this paper, we present a 16-channel neural spike detection ASIC. The chip takes raw data as inputs, and outputs three data streams simultaneously: field potentials down sampled at 1.25 KHz, band-pass filtered neural data, and spiking probability maps sampled at 40 KHz. The functionality and the performance of the chip have been verified in both in-vivo and benchtop experiments. Fabricated in a 0.13 μm CMOS process, the chip has a peak power dissipation of 85 μW per channel and achieves a data-rate reduction of 98.44%. © 2013 IEEE.|
|Source Title:||Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS|
|Appears in Collections:||Staff Publications|
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