Please use this identifier to cite or link to this item: https://doi.org/10.1109/JSSC.2005.857421
Title: A CMOS TV tuner/demodulator IC with digital image rejection
Authors: Heng, C.-H. 
Gupta, M.
Lee, S.-H.
Kang, D.
Song, B.-S.
Keywords: Direct conversion receivers
Frequency synthe-sizers
Image rejection
Low-IF receivers
TV receiver tuners
Vector processing
Zero-IF receivers
Issue Date: Dec-2005
Citation: Heng, C.-H., Gupta, M., Lee, S.-H., Kang, D., Song, B.-S. (2005-12). A CMOS TV tuner/demodulator IC with digital image rejection. IEEE Journal of Solid-State Circuits 40 (12) : 2525-2535. ScholarBank@NUS Repository. https://doi.org/10.1109/JSSC.2005.857421
Abstract: Superheterodyne TV tuners have been implemented in discrete forms using tunable RF and SAW IF filters. Integrating TV tuners in CMOS technology without them is a challenging task to cope with technical issues such as harmonic mixing and image. The image rejection in low- or zero-IF systems has been limited to 30-40 dB by analog imperfections such as I/Q path gain and phase mismatches. A single-chip low-IF TV tuner solution is proposed so that the image can be suppressed digitally using an image cancellation technique based on a complex one-tap LMS signal decorrelation algorithm. Programmable digital filtering and video/sound demodulation make a multistandard TV tuner feasible in the 48-860 MHz VHF/UHF band. The chip has a maximum gain of 63 dB and an input automatic gain control (AGC) range from -15 to 25 dB with 0.85-dB steps. It achieves an image and IF rejection of 60 dB, a peak carrier-to-noise ratio (CNR) of 55 dB, and a peak sound signal-to-noise ratio (SNR) of 44 dB without frequency modulation (FM) de-emphasis. The prototype occupies 6 × 6 mm 2 in 0.25-μm CMOS and consumes 1 W at 2.5 V. © 2005 IEEE.
Source Title: IEEE Journal of Solid-State Circuits
URI: http://scholarbank.nus.edu.sg/handle/10635/83338
ISSN: 00189200
DOI: 10.1109/JSSC.2005.857421
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