Please use this identifier to cite or link to this item:
|Title:||A 50 μw/Ch artifacts-insensitive neural recorder using frequency-shaping technique|
|Citation:||Xu, J.,Yang, Z. (2013-11-07). A 50 μw/Ch artifacts-insensitive neural recorder using frequency-shaping technique. Proceedings of the Custom Integrated Circuits Conference : -. ScholarBank@NUS Repository. https://doi.org/10.1109/CICC.2013.6658532|
|Abstract:||This paper presents a frequency-shaping (FS) neural recording interface that can inherently reject electrode offset, 5-10 times increase input impedance, 4.5-bit extend system dynamic range (DR), and provide much more tolerance to motion artifacts and 50/60 Hz power noise interferences. It is supposed to be more suitable for long-term brain-machine-interface (BMI) experiments. To achieve the mentioned performance above, the proposed architecture adopts an auto-zero offset calibration to avoid system saturation, a delayed-signaling noise cancellation to attenuate kT/C noise, and an automatical data-splitting technique to reduce input-referred noise at low frequencies. Measured at a 40 kHz sampling clock and ± 0.6 V supply, the recorder consumes 50 μW/ch, including 22 μW for FS amplifier, 12 μW for gain-stage amplifier, 12 μW for buffer, and 4 μW for successive approximation register (SAR) analog-to-digital converter (ADC). The designed SAR ADC achieves an effective-number-of-bit (ENOB) of 11-bit in a 160 kHz bandwidth. In addition, the recorder has a 3 pF input capacitance and 15.5-bit (11-bit+4.5-bit) system DR due to the utilization of FS technique. The designed chip occupies 0.76 mm2/ch in a 0.13 μm CMOS process. © 2013 IEEE.|
|Source Title:||Proceedings of the Custom Integrated Circuits Conference|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Oct 15, 2018
checked on Oct 5, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.