Please use this identifier to cite or link to this item: https://doi.org/10.1109/VLSIT.2008.4588554
Title: 5 nm gate length nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation technique
Authors: Liow, T.-Y.
Tan, K.-M.
Lee, R.T.P. 
Zhu, M. 
Tan, B.L.-H.
Samudra, G.S. 
Balasubramanian, N.
Yeo, Y.-C. 
Issue Date: 2008
Citation: Liow, T.-Y.,Tan, K.-M.,Lee, R.T.P.,Zhu, M.,Tan, B.L.-H.,Samudra, G.S.,Balasubramanian, N.,Yeo, Y.-C. (2008). 5 nm gate length nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation technique. Digest of Technical Papers - Symposium on VLSI Technology : 36-37. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSIT.2008.4588554
Abstract: We report the first demonstration of pure Ge source/drain (S/D) stressors (unembedded) on the ultra-narrow or ultra-thin Si S/D regions of Nanowire-FETs and UTB-FETs, compressively straining the channels to provide up to ∼100% IDsat enhancement. Devices with 5 nm gate lengths were fabricated. In addition, we report a novel Melt-Enhanced Dopant (MeltED) diffusion and activation technique to form embedded Ge S/D stressor in the S/D regions of nanowire-FETs, boosting the channel strain even further, and achieving ∼125% I Dsat enhancement. © 2008 IEEE.
Source Title: Digest of Technical Papers - Symposium on VLSI Technology
URI: http://scholarbank.nus.edu.sg/handle/10635/83300
ISBN: 9781424418053
ISSN: 07431562
DOI: 10.1109/VLSIT.2008.4588554
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