Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2007.891757
Title: Wide Vfband Vth tunability for metal-gated MOS devices with HfLaO gate dielectrics
Authors: Wang, X.P.
Yu, H.Y.
Li, M.-F. 
Zhu, C.X. 
Biesemans, S.
Chin, A.
Sun, Y.Y.
Feng, Y.P. 
Lim, A.
Yeo, Y.-C. 
Loh, W.Y.
Lo, G.Q.
Kwong, D.-L.
Keywords: CMOS
Fermi-level pinning
HfLaO
High-k (HK) dielectric
Interfacial dipole
Metal gate (MG)
Work function
Issue Date: Apr-2007
Source: Wang, X.P., Yu, H.Y., Li, M.-F., Zhu, C.X., Biesemans, S., Chin, A., Sun, Y.Y., Feng, Y.P., Lim, A., Yeo, Y.-C., Loh, W.Y., Lo, G.Q., Kwong, D.-L. (2007-04). Wide Vfband Vth tunability for metal-gated MOS devices with HfLaO gate dielectrics. IEEE Electron Device Letters 28 (4) : 258-260. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2007.891757
Abstract: For the first time, we demonstrate experimentally that by using HfLaO high-k gate dielectric, the flat-band voltage (Vfb) and the threshold voltage (Vth) of metal-electrode-gated MOS devices can be tuned effectively in a wide range (wider than that from the Si-conduction band edge to the Si-valence band edge) after a 1000-°C annealing required by a conventional CMOS source/drain activation process. As prototype examples shown in this letter, TaN gate with effective work function Φm,eff ∼ 3.9-4.2 eV and Pt gate with Φm,eff ∼ 5.5 eV are reported. A specific model based on the interfacial dipole between the metal gate and the HfLaO is proposed to interpret the results. This provides an additionally practical guideline for choosing the appropriate gate stacks and dielectric to meet the requirements of future CMOS devices. © 2007 IEEE.
Source Title: IEEE Electron Device Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/83267
ISSN: 07413106
DOI: 10.1109/LED.2007.891757
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