Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2004.841861
Title: Three-dimensional metal gate-high-Κ-GOI CMOSFETs on 1-poly-6-metal 0.18-μm Si devices
Authors: Yu, D.S.
Chin, A. 
Liao, C.C.
Lee, C.F.
Cheng, C.F.
Li, M.F. 
Yoo, W.J. 
McAlister, S.P.
Keywords: Ge-on-insulator (GOI)
LaA1O3
Metal-gate
MOSFET
Three-dimensional (3-D)
Issue Date: Feb-2005
Citation: Yu, D.S., Chin, A., Liao, C.C., Lee, C.F., Cheng, C.F., Li, M.F., Yoo, W.J., McAlister, S.P. (2005-02). Three-dimensional metal gate-high-Κ-GOI CMOSFETs on 1-poly-6-metal 0.18-μm Si devices. IEEE Electron Device Letters 26 (2) : 118-120. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2004.841861
Abstract: We demonstrate three-dimensional (3-D) self-aligned [IrO2-IrO2-Hf]-LaAlO3-Ge-on-insulator (GOI) CMOSFETs above 0.18-μm Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2-LaAlO 3-GOI p-MOSFETs and IrO2-Hf-LaAlO 3-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm2/Vs respectively, without depredating the underneath 0.18-μm Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI. © 2005 IEEE.
Source Title: IEEE Electron Device Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/83205
ISSN: 07413106
DOI: 10.1109/LED.2004.841861
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