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|Title:||Tensile-strained germanium CMOS integration on silicon|
CMOS integrated circuits
|Citation:||Zang, H., Loh, W.Y., Ye, J.D., Lo, G.Q., Cho, B.J. (2007-12). Tensile-strained germanium CMOS integration on silicon. IEEE Electron Device Letters 28 (12) : 1117-1119. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2007.909836|
|Abstract:||Monolithic integration of tensile-strained Si/Germanium (Ge)-channel n-MOS and tensile-strained Ge p-MOS with ultrathin (equivalent oxide thickness ∼14 ̊A) HfO2 gate dielectric and TaN gate stack on Si substrate is demonstrated. Defect-free Ge layer (279 nm) grown by ultrahigh vacuum chemical-vapor deposition is achieved using a two-step Ge-growth technique coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to ∼ 0.67% and exhibits a peak hole mobility of 250 cm2/V · s which is 100% higher than the universal Si hole mobility. The gate leakage current is two orders of magnitude lower compared to the reported results on Ge bulk. © 2007 IEEE.|
|Source Title:||IEEE Electron Device Letters|
|Appears in Collections:||Staff Publications|
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