Please use this identifier to cite or link to this item: https://doi.org/10.1021/nl073407b
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dc.titleSub-100 nanometer channel length Ge/Si nanowire transistors with potential for 2 THz switching speed
dc.contributor.authorHu, Y.
dc.contributor.authorXiang, J.
dc.contributor.authorLiang, G.
dc.contributor.authorYan, H.
dc.contributor.authorLieber, C.M.
dc.date.accessioned2014-10-07T04:37:21Z
dc.date.available2014-10-07T04:37:21Z
dc.date.issued2008-03
dc.identifier.citationHu, Y., Xiang, J., Liang, G., Yan, H., Lieber, C.M. (2008-03). Sub-100 nanometer channel length Ge/Si nanowire transistors with potential for 2 THz switching speed. Nano Letters 8 (3) : 925-930. ScholarBank@NUS Repository. https://doi.org/10.1021/nl073407b
dc.identifier.issn15306984
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83107
dc.description.abstractGe/Si core/shell nanowires (NWs) are attractive and flexible building blocks for nanoelectronics ranging from field-effect transistors (FETs) to low-temperature quantum devices. Here we report the first studies of the size-dependent performance limits of Ge/Si NWFETs in the sub-100 nm channel length regime. Metallic nanoscale electrical contacts were made and used to define sub-100 nm Ge/Si channels by controlled solid-state conversion of Ge/Si NWs to NiSi xGe y alloys. Electrical transport measurements and modeling studies demonstrate that the nanoscale metallic contacts overcome deleterious short-channel effects present in lithographically defined sub-100 nm channels. Data acquired on 70 and 40 nm channel length Ge/Si NWFETs with a drain-source bias of 0.5 V yield transconductance values of 78 and 91 μS, respectively, and maximum on-currents of 121 and 152 μA. The scaled transconductance and on-current values for a gate and bias voltage window of 0.5 V were 6.2 mS/μm and 2.1 mA/μm, respectively, for the 40 nm device and exceed the best reported values for planar Si and NW p-type FETs. In addition, analysis of the intrinsic switching delay shows that terahertz intrinsic operation speed is possible when channel length is reduced to 70 nm and that an intrinsic delay of 0.5 ps is achievable in our 40 nm device. Comparison of the experimental data with simulations based on a semiclassical, ballistic transport model suggests that these sub-100 nm Ge/Si NWFETs with integrated high-κ gate dielectric operate near the ballistic limit. © 2008 American Chemical Society.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1021/nl073407b
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1021/nl073407b
dc.description.sourcetitleNano Letters
dc.description.volume8
dc.description.issue3
dc.description.page925-930
dc.identifier.isiut000253947400029
Appears in Collections:Staff Publications

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