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|Title:||Strained-SOI n-channel transistor with silicon-carbon source/drain regions for carrier transport enhancement|
|Source:||Chui, K.-J., Ang, K.-W., Chin, H.-C., Shen, C., Wong, L.-Y., Tung, C.-H., Balasubramanian, N., Li, M.F., Samudra, G.S., Yeo, Y.-C. (2006-09). Strained-SOI n-channel transistor with silicon-carbon source/drain regions for carrier transport enhancement. IEEE Electron Device Letters 27 (9) : 778-780. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2006.881083|
|Abstract:||A novel 80 nm gate length strained-Si n-channel transistor structure with lattice-mismatched source and drain (S/D) formed on thin-body silicon-on-insulator substrate is reported. The strained transistor features silicon-carbon (Si1-yCy) S/D regions, which are pseudomorphically grown by selective epitaxy. The incorporated carbon mole fraction y is 0.01. The lattice mismatch between Si0.99C0.01 and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The implementation of the Si0.99C0.01 stressors provides a substantial drive current IDsat enhancement of 11% over a control transistor at a gate length of 80 nm and a width of ∼ 1.1 μm, while the enhancement for the linear drive current IDlin is approximately two times larger. Pulse measurements were also performed to correct for self-heating effects. © 2006 IEEE.|
|Source Title:||IEEE Electron Device Letters|
|Appears in Collections:||Staff Publications|
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