Please use this identifier to cite or link to this item: https://doi.org/10.1109/TED.2009.2028402
Title: Self-consistent Schrödinger-Poisson simulations on capacitance-voltage characteristics of silicon nanowire gate-all-around MOS devices with experimental comparisons
Authors: Chin, S.K.
Ligatchev, V.
Rustagi, S.C.
Zhao, H.
Samudra, G.S. 
Singh, N.
Lo, G.Q.
Kwong, D.-L.
Keywords: Capacitance
Gate-all-around
MOS
Schrödinger-Poisson (SP)
Silicon (Si) nanowire
Issue Date: 2009
Citation: Chin, S.K., Ligatchev, V., Rustagi, S.C., Zhao, H., Samudra, G.S., Singh, N., Lo, G.Q., Kwong, D.-L. (2009). Self-consistent Schrödinger-Poisson simulations on capacitance-voltage characteristics of silicon nanowire gate-all-around MOS devices with experimental comparisons. IEEE Transactions on Electron Devices 56 (10) : 2312-2318. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2009.2028402
Abstract: We simulate room temperature capacitance-voltage characteristics of silicon (Si) nanowire gate-all-around MOS structures with radius ≤ 10 nm using a self-consistent Schrödinger-Poisson solver in cylindrical coordinates with full treatment of the transverse quantum confinement. In this paper, we compare our simulation results with the latest capacitance measurements on single Si nanowire pMOS and nMOS devices in the subfemtofarad range. We also propose to probe the density-of-states features of the Si channel from the capacitance-voltage characteristics at room temperature measurements using dC/dV dependence and illustrate the idea by employing the latest measurements, our quantum and Medici (Synopsys) simulations, as well as a simplified analytical model. © 2009 IEEE.
Source Title: IEEE Transactions on Electron Devices
URI: http://scholarbank.nus.edu.sg/handle/10635/83005
ISSN: 00189383
DOI: 10.1109/TED.2009.2028402
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