Please use this identifier to cite or link to this item: https://doi.org/10.1109/TVLSI.2007.893621
Title: Relaxed K-best MIMO signal detector design and VLSI implementation
Authors: Chen, S.
Zhang, T.
Xin, Y. 
Keywords: Detection
Maximum likelihood (ML)
Multiple-input multiple-output (MIMO) systems
Spatial multiplexing
VLSI
Issue Date: Mar-2007
Citation: Chen, S., Zhang, T., Xin, Y. (2007-03). Relaxed K-best MIMO signal detector design and VLSI implementation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (3) : 328-337. ScholarBank@NUS Repository. https://doi.org/10.1109/TVLSI.2007.893621
Abstract: Signal detector is a key element in a multiple-input multiple-output (MIMO) wireless communication receiver. It has been well demonstrated that nonlinear tree search MIMO detectors can achieve near-optimum detection performance, nevertheless their efficient high-speed VLSI implementations are not trivial. For example, the hardware design of hard- or soft- output detectors for a 4 × 4 MIMO system with 64 quadrature amplitude modulation (QAM) still remains missing in the open literature. As an attempt to tackle this challenge, this paper presents an implementation-oriented breadth-first tree search MIMO detector design solution. The key is to appropriately modify the conventional breadth-first tree search detection algorithm in order to largely improve the suitability for efficient hardware implementation, while maintaining good detection performance. To demonstrate the effectiveness of the proposed design solution, using 0.13-μm CMOS standard cell and memory libraries, we designed a soft-output signal detector for 4 × 4 MIMO with 64-QAM. With the silicon area of about 31 mm2, the detector can achieve above 100 Mb/s and realize the performance very close to that of the sphere decoding algorithm. © 2007 IEEE.
Source Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/82974
ISSN: 10638210
DOI: 10.1109/TVLSI.2007.893621
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