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https://doi.org/10.1109/TED.2007.900680
| Title: | P-Type floating gate for retention and P/E window improvement of flash memory devices |
| Authors: | Shen, C. Pu, J. Li, M.-F. Cho, B.J. |
| Keywords: | Coupling ratio (CR) Electrically erasable programmable read-only memory (EEPROM) Flash memory Floating gate P-type Retention |
| Issue Date: | Aug-2007 |
| Citation: | Shen, C., Pu, J., Li, M.-F., Cho, B.J. (2007-08). P-Type floating gate for retention and P/E window improvement of flash memory devices. IEEE Transactions on Electron Devices 54 (8) : 1910-1917. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2007.900680 |
| Abstract: | A Flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) Vth window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled Flash memory cells. Both device simulation and experimental verification are presented. © 2007 IEEE. |
| Source Title: | IEEE Transactions on Electron Devices |
| URI: | http://scholarbank.nus.edu.sg/handle/10635/82943 |
| ISSN: | 00189383 |
| DOI: | 10.1109/TED.2007.900680 |
| Appears in Collections: | Staff Publications |
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